4 * Board functions for B&R KWB Board
6 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
27 #include <power/tps65217.h>
28 #include "../common/bur_common.h"
31 /* -------------------------------------------------------------------------*/
32 /* -- defines for used GPIO Hardware -- */
33 #define ESC_KEY (0+19)
35 #define PUSH_KEY (0+31)
36 /* -------------------------------------------------------------------------*/
37 /* -- PSOC Resetcontroller Register defines -- */
39 /* I2C Address of controller */
40 #define RSTCTRL_ADDR 0x75
41 /* Register for CTRL-word */
42 #define RSTCTRL_CTRLREG 0x01
43 /* Register for giving some information to VxWorks OS */
44 #define RSTCTRL_SCRATCHREG 0x04
46 /* -- defines for RSTCTRL_CTRLREG -- */
47 #define RSTCTRL_FORCE_PWR_NEN 0x0404
48 #define RSTCTRL_CAN_STB 0x4040
50 DECLARE_GLOBAL_DATA_PTR;
52 #if defined(CONFIG_SPL_BUILD)
53 /* TODO: check ram-timing ! */
54 static const struct ddr_data ddr3_data = {
55 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
56 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
57 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
58 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
60 static const struct cmd_control ddr3_cmd_ctrl_data = {
61 .cmd0csratio = MT41K256M16HA125E_RATIO,
62 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
64 .cmd1csratio = MT41K256M16HA125E_RATIO,
65 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
67 .cmd2csratio = MT41K256M16HA125E_RATIO,
68 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
70 static struct emif_regs ddr3_emif_reg_data = {
71 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
72 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
73 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
74 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
75 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
76 .zq_config = MT41K256M16HA125E_ZQ_CFG,
77 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
80 static const struct ctrl_ioregs ddr3_ioregs = {
81 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
82 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
83 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
84 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
85 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
88 #define OSC (V_OSCK/1000000)
89 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
91 void am33xx_spl_board_init(void)
93 unsigned int oldspeed;
96 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
97 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
99 * enable additional clocks of modules which are accessed later from
102 u32 *const clk_domains[] = { 0 };
104 u32 *const clk_modules_kwbspecific[] = {
105 &cmwkup->wkup_adctscctrl,
107 &cmper->dcan0clkctrl,
108 &cmper->dcan1clkctrl,
109 &cmper->epwmss0clkctrl,
110 &cmper->epwmss1clkctrl,
111 &cmper->epwmss2clkctrl,
113 &cmper->lcdcclkstctrl,
116 do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
117 /* setup LCD-Pixel Clock */
118 writel(0x2, CM_DPLL + 0x34);
119 /* power-OFF LCD-Display */
120 gpio_direction_output(LCD_PWR, 0);
123 enable_i2c_pin_mux();
125 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
127 /* power-ON 3V3 via Resetcontroller */
128 oldspeed = i2c_get_bus_speed();
129 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
130 buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
131 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
132 (uint8_t *)&buf, sizeof(buf));
133 i2c_set_bus_speed(oldspeed);
135 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
141 const struct dpll_params *get_dpll_ddr_params(void)
146 void sdram_init(void)
148 config_ddr(400, &ddr3_ioregs,
151 &ddr3_emif_reg_data, 0);
153 #endif /* CONFIG_SPL_BUILD */
155 * Basic board specific setup. Pinmux has been handled already.
163 #ifdef CONFIG_BOARD_LATE_INIT
164 int board_late_init(void)
166 const unsigned int toff = 1000;
167 unsigned int cnt = 3;
168 unsigned short buf = 0xAAAA;
169 unsigned char scratchreg = 0;
170 unsigned int oldspeed;
172 /* try to read out some boot-instruction from resetcontroller */
173 oldspeed = i2c_get_bus_speed();
174 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
175 i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
176 &scratchreg, sizeof(scratchreg));
177 i2c_set_bus_speed(oldspeed);
179 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
182 if (gpio_get_value(ESC_KEY)) {
184 lcd_position_cursor(1, 8);
188 "release ESC-KEY to enter SERVICE-mode.");
192 "release ESC-KEY to enter DIAGNOSE-mode.");
196 "release ESC-KEY to enter BOOT-mode. ");
201 if (!gpio_get_value(ESC_KEY) &&
202 gpio_get_value(PUSH_KEY) && 2 == cnt) {
203 lcd_position_cursor(1, 8);
205 "switching to network-console ... ");
206 setenv("bootcmd", "run netconsole");
209 } else if (!gpio_get_value(ESC_KEY) &&
210 gpio_get_value(PUSH_KEY) && 1 == cnt) {
211 lcd_position_cursor(1, 8);
213 "starting u-boot script from USB ... ");
214 setenv("bootcmd", "run usbscript");
217 } else if ((!gpio_get_value(ESC_KEY) &&
218 gpio_get_value(PUSH_KEY) && cnt == 0) ||
219 (gpio_get_value(ESC_KEY) &&
220 gpio_get_value(PUSH_KEY) && cnt == 0)) {
221 lcd_position_cursor(1, 8);
223 "starting script from network ... ");
224 setenv("bootcmd", "run netscript");
227 } else if (!gpio_get_value(ESC_KEY)) {
231 } else if (scratchreg == 0xCC) {
232 lcd_position_cursor(1, 8);
234 "starting vxworks from network ... ");
235 setenv("bootcmd", "run netboot");
237 } else if (scratchreg == 0xCD) {
238 lcd_position_cursor(1, 8);
240 "starting script from network ... ");
241 setenv("bootcmd", "run netscript");
243 } else if (scratchreg == 0xCE) {
244 lcd_position_cursor(1, 8);
246 "starting AR from eMMC ... ");
247 setenv("bootcmd", "run mmcboot");
251 lcd_position_cursor(1, 8);
254 lcd_puts("entering BOOT-mode. ");
255 setenv("bootcmd", "run defaultAR");
259 lcd_puts("entering DIAGNOSE-mode. ");
263 lcd_puts("entering SERVICE mode. ");
267 lcd_puts("loading OS... ");
271 /* write bootinfo into scratchregister of resetcontroller */
272 oldspeed = i2c_get_bus_speed();
273 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
274 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
275 (uint8_t *)&buf, sizeof(buf));
276 i2c_set_bus_speed(oldspeed);
278 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
280 /* setup othbootargs for bootvx-command (vxWorks bootline) */
281 char othbootargs[128];
282 snprintf(othbootargs, sizeof(othbootargs),
283 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
284 (unsigned int) gd->fb_base-0x20,
285 (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
286 (u32)getenv_ulong("vx_romfsbase", 16, 0),
287 (u32)getenv_ulong("vx_romfssize", 16, 0));
288 setenv("othbootargs", othbootargs);
290 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
291 * expect that vectors are there, original u-boot moves them to _start
293 __asm__("ldr r0,=0x20000");
294 __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
298 #endif /* CONFIG_BOARD_LATE_INIT */