board/altera/socfpga/socfpga.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/reset_manager.h>
   9 #include <asm/io.h>
  10
  11 #include <usb.h>
  12 #include <usb/s3c_udc.h>
  13 #include <usb_mass_storage.h>
  14
  15 #include <micrel.h>
  16 #include <netdev.h>
  17 #include <phy.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /*
  22  * Initialization function which happen at early stage of c code
  23  */
  24 int board_early_init_f(void)
  25 {
  26         return 0;
  27 }
  28
  29 /*
  30  * Miscellaneous platform dependent initialisations
  31  */
  32 int board_init(void)
  33 {
  34         /* Address of boot parameters for ATAG (if ATAG is used) */
  35         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  36
  37         return 0;
  38 }
  39
  40 /*
  41  * PHY configuration
  42  */
  43 #ifdef CONFIG_PHY_MICREL_KSZ9021
  44 int board_phy_config(struct phy_device *phydev)
  45 {
  46         int ret;
  47         /*
  48          * These skew settings for the KSZ9021 ethernet phy is required for ethernet
  49          * to work reliably on most flavors of cyclone5 boards.
  50          */
  51         ret = ksz9021_phy_extended_write(phydev,
  52                                          MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  53                                          0x0);
  54         if (ret)
  55                 return ret;
  56
  57         ret = ksz9021_phy_extended_write(phydev,
  58                                          MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
  59                                          0x0);
  60         if (ret)
  61                 return ret;
  62
  63         ret = ksz9021_phy_extended_write(phydev,
  64                                          MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  65                                          0xf0f0);
  66         if (ret)
  67                 return ret;
  68
  69         if (phydev->drv->config)
  70                 return phydev->drv->config(phydev);
  71
  72         return 0;
  73 }
  74 #endif
  75
  76 #ifdef CONFIG_USB_GADGET
  77 struct s3c_plat_otg_data socfpga_otg_data = {
  78         .regs_otg       = CONFIG_USB_DWC2_REG_ADDR,
  79         .usb_gusbcfg    = 0x1417,
  80 };
  81
  82 int board_usb_init(int index, enum usb_init_type init)
  83 {
  84         return s3c_udc_probe(&socfpga_otg_data);
  85 }
  86
  87 int g_dnl_board_usb_cable_connected(void)
  88 {
  89         return 1;
  90 }
  91 #endif