2 * This is the main board level file for the Redwood AMCC board.
5 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/ppc4xx.h>
30 #include <asm/processor.h>
34 int compare_to_true(char *str);
35 char *remove_l_w_space(char *in_str);
36 char *remove_t_w_space(char *in_str);
37 int get_console_port(void);
39 static void early_init_EBC(void);
40 static int bootdevice_selected(void);
41 static void early_reinit_EBC(int);
42 static void early_init_UIC(void);
47 #define BOOT_FROM_8BIT_SRAM 0x00
48 #define BOOT_FROM_16BIT_SRAM 0x01
49 #define BOOT_FROM_32BIT_SRAM 0x02
50 #define BOOT_FROM_8BIT_NAND 0x03
51 #define BOOT_FROM_16BIT_NOR 0x04
52 #define BOOT_DEVICE_UNKNOWN 0xff
55 * EBC Devices Characteristics
56 * Peripheral Bank Access Parameters - EBC_BxAP
57 * Peripheral Bank Configuration Register - EBC_BxCR
63 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
64 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
65 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
67 #define EBC_BXAP_8BIT_SRAM \
68 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
69 EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
70 EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
71 EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
72 EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
73 EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
76 #define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
77 #define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
82 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
83 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
84 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
86 #define EBC_BXAP_NAND \
87 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
88 EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
89 EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
90 EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
91 EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
92 EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
98 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
99 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
100 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
102 #define EBC_BXAP_NOR \
103 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
104 EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
105 EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
106 EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
107 EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
108 EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
109 EBC_BXAP_PEN_DISABLED
114 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
115 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
117 #define EBC_BXAP_FPGA \
118 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \
119 EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
120 EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \
121 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \
122 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \
123 EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \
124 EBC_BXAP_PEN_DISABLED
126 #define EBC_BXCR_8BIT_SRAM_CS0 \
127 EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \
128 EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
130 #define EBC_BXCR_32BIT_SRAM_CS0 \
131 EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \
132 EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
134 #define EBC_BXCR_NAND_CS0 \
135 EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
136 EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
138 #define EBC_BXCR_16BIT_SRAM_CS0 \
139 EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \
140 EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
142 #define EBC_BXCR_NOR_CS0 \
143 EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
144 EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
146 #define EBC_BXCR_NOR_CS1 \
147 EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
148 EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
150 #define EBC_BXCR_NAND_CS1 \
151 EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
152 EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
154 #define EBC_BXCR_NAND_CS2 \
155 EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \
156 EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
158 #define EBC_BXCR_SRAM_CS2 \
159 EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \
160 EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
162 #define EBC_BXCR_LARGE_FLASH_CS2 \
163 EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \
164 EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
166 #define EBC_BXCR_FPGA_CS3 \
167 EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \
168 EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
170 /*****************************************************************************
171 * UBOOT initiated board specific function calls
172 ****************************************************************************/
174 int board_early_init_f(void)
176 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
184 * Determine which boot device was selected
186 computed_boot_device = bootdevice_selected();
189 * Reinit EBC based on selected boot device
191 early_reinit_EBC(computed_boot_device);
194 * Setup for UIC on 460SX redwood board
204 int i = getenv_f("serial#", buf, sizeof(buf));
206 printf("Board: Redwood - AMCC 460SX Reference Board");
216 static void early_init_EBC(void)
219 * Initialize EBC CONFIG -
220 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
222 * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
224 mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
226 EBC_CFG_RTC_16PERCLK |
227 EBC_CFG_ATC_PREVIOUS |
228 EBC_CFG_DTC_PREVIOUS |
229 EBC_CFG_CTC_PREVIOUS |
230 EBC_CFG_OEO_PREVIOUS |
231 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
234 * PART 1 : Initialize EBC Bank 3
235 * ==============================
236 * Bank1 is always associated to the EPLD.
237 * It has to be initialized prior to other banks settings computation
238 * since some board registers values may be needed to determine the
241 mtebc(PB1AP, EBC_BXAP_FPGA);
242 mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
246 static int bootdevice_selected(void)
248 unsigned long sdr0_pinstp;
249 unsigned long bootstrap_settings;
250 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
253 * Determine which boot device was selected
254 * =================================================
256 * Read Pin Strap Register in PPC460SX
257 * Result can either be :
258 * - Boot strap = boot from EBC 8bits => Small Flash
259 * - Boot strap = boot from PCI
261 * In case of boot from IIC, read Serial Device Strap Register1
263 * Result can either be :
264 * - Boot from EBC - EBC Bus Width = 8bits => Small Flash
265 * - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
269 /* Read Pin Strap Register in PPC460SX */
270 mfsdr(SDR0_PINSTP, sdr0_pinstp);
271 bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
273 switch (bootstrap_settings) {
274 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
276 * Boot from SRAM, 8bit width
278 computed_boot_device = BOOT_FROM_8BIT_SRAM;
280 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
282 * Boot from SRAM, 32bit width
284 computed_boot_device = BOOT_FROM_32BIT_SRAM;
286 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
288 * Boot from NAND, 8bit width
290 computed_boot_device = BOOT_FROM_8BIT_NAND;
292 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
294 * Boot from SRAM, 16bit width
295 * Boot setting in IIC EEPROM 0x50
297 computed_boot_device = BOOT_FROM_16BIT_SRAM;
299 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
301 * Boot from NOR, 16bit width
302 * Boot setting in IIC EEPROM 0x54
304 computed_boot_device = BOOT_FROM_16BIT_NOR;
308 computed_boot_device = BOOT_DEVICE_UNKNOWN;
312 return computed_boot_device;
315 static void early_reinit_EBC(int computed_boot_device)
318 * Compute EBC settings depending on selected boot device
319 * ======================================================
321 * Resulting EBC init will be among following configurations :
323 * - Boot from EBC 8bits => boot from Small Flash selected
324 * EBC-CS0 = Small Flash
325 * EBC-CS2 = Large Flash and SRAM
327 * - Boot from EBC 16bits => boot from Large Flash or SRAM
328 * EBC-CS0 = Large Flash or SRAM
329 * EBC-CS2 = Small Flash
332 * EBC-CS0 = not initialized to avoid address contention
333 * EBC-CS2 = same as boot from Small Flash selected
336 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
337 unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
338 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
340 switch (computed_boot_device) {
341 /*-------------------------------------------------------------------*/
342 case BOOT_FROM_8BIT_SRAM:
343 /*-------------------------------------------------------------------*/
344 ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
345 ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
346 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
347 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
348 ebc0_cs2_bxap_value = EBC_BXAP_NAND;
349 ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
352 /*-------------------------------------------------------------------*/
353 case BOOT_FROM_16BIT_SRAM:
354 /*-------------------------------------------------------------------*/
355 ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
356 ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
357 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
358 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
359 ebc0_cs2_bxap_value = EBC_BXAP_NAND;
360 ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
363 /*-------------------------------------------------------------------*/
364 case BOOT_FROM_32BIT_SRAM:
365 /*-------------------------------------------------------------------*/
366 ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
367 ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
368 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
369 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
370 ebc0_cs2_bxap_value = EBC_BXAP_NAND;
371 ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
374 /*-------------------------------------------------------------------*/
375 case BOOT_FROM_16BIT_NOR:
376 /*-------------------------------------------------------------------*/
377 ebc0_cs0_bxap_value = EBC_BXAP_NOR;
378 ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
379 ebc0_cs1_bxap_value = EBC_BXAP_NAND;
380 ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
381 ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
382 ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
385 /*-------------------------------------------------------------------*/
386 case BOOT_FROM_8BIT_NAND:
387 /*-------------------------------------------------------------------*/
388 ebc0_cs0_bxap_value = EBC_BXAP_NAND;
389 ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
390 ebc0_cs1_bxap_value = EBC_BXAP_NOR;
391 ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
392 ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
393 ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
396 /*-------------------------------------------------------------------*/
398 /*-------------------------------------------------------------------*/
399 /* BOOT_DEVICE_UNKNOWN */
403 mtebc(PB0AP, ebc0_cs0_bxap_value);
404 mtebc(PB0CR, ebc0_cs0_bxcr_value);
405 mtebc(PB1AP, ebc0_cs1_bxap_value);
406 mtebc(PB1CR, ebc0_cs1_bxcr_value);
407 mtebc(PB2AP, ebc0_cs2_bxap_value);
408 mtebc(PB2CR, ebc0_cs2_bxcr_value);
411 static void early_init_UIC(void)
414 * Initialise UIC registers. Clear all interrupts. Disable all
416 * Set critical interrupt values. Set interrupt polarities. Set
417 * interrupt trigger levels. Make bit 0 High priority. Clear all
420 mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
421 mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
422 mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
424 mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
425 mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
426 mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
427 mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
429 mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
430 mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
431 mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
433 mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
434 mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
435 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
436 mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
438 mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
439 mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
440 mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
442 mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
443 mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
444 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
445 mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
447 mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
448 mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
449 * cascade to be checked */
450 mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
452 mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
453 mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
454 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
455 mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */