board/apollon/apollon.c

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Samsung Electronics.
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  *
   6  * Derived from omap2420
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26 #include <common.h>
  27 #include <asm/arch/omap2420.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/bits.h>
  30 #include <asm/arch/mux.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/arch/sys_info.h>
  33 #include <asm/arch/mem.h>
  34 #include <i2c.h>
  35 #include <asm/mach-types.h>
  36
  37 void wait_for_command_complete(unsigned int wd_base);
  38
  39 /*******************************************************
  40  * Routine: delay
  41  * Description: spinning delay to use before udelay works
  42 ******************************************************/
  43 static inline void delay(unsigned long loops) {
  44         __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  45                           "bne 1b":"=r" (loops):"0"(loops)); }
  46
  47 /*****************************************
  48  * Routine: board_init
  49  * Description: Early hardware init.
  50  *****************************************/
  51 int board_init(void)
  52 {
  53         DECLARE_GLOBAL_DATA_PTR;
  54
  55         gpmc_init();            /* in SRAM or SDRM, finish GPMC */
  56
  57         gd->bd->bi_arch_number = 919;
  58         /* adress of boot parameters */
  59         gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
  60
  61         return 0;
  62 }
  63
  64 /**********************************************************
  65  * Routine: s_init
  66  * Description: Does early system init of muxing and clocks.
  67  * - Called path is with sram stack.
  68  **********************************************************/
  69 void s_init(void)
  70 {
  71
  72         watchdog_init();
  73         set_muxconf_regs();
  74         delay(100);
  75
  76         peripheral_enable();
  77         icache_enable();
  78 }
  79
  80 /*******************************************************
  81  * Routine: misc_init_r
  82  * Description: Init ethernet (done here so udelay works)
  83 ********************************************************/
  84 int misc_init_r(void)
  85 {
  86         ether_init();           /* better done here so timers are init'ed */
  87         return (0);
  88 }
  89
  90 /****************************************
  91  * Routine: watchdog_init
  92  * Description: Shut down watch dogs
  93  *****************************************/
  94 void watchdog_init(void)
  95 {
  96         /* There are 4 watch dogs.  1 secure, and 3 general purpose.
  97          * The ROM takes care of the secure one. Of the 3 GP ones,
  98          * 1 can reset us directly, the other 2 only generate MPU interrupts.
  99          */
 100         __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
 101         wait_for_command_complete(WD2_BASE);
 102         __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
 103
 104 #define MPU_WD_CLOCKED 1
 105 #if MPU_WD_CLOCKED              /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
 106         __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
 107         wait_for_command_complete(WD3_BASE);
 108         __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
 109
 110         __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
 111         wait_for_command_complete(WD4_BASE);
 112         __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
 113 #endif
 114 }
 115
 116 /******************************************************
 117  * Routine: wait_for_command_complete
 118  * Description: Wait for posting to finish on watchdog
 119 ******************************************************/
 120 void wait_for_command_complete(unsigned int wd_base) {
 121         int pending = 1;
 122         do {
 123                 pending = __raw_readl(wd_base + WWPS);
 124         } while (pending);
 125 }
 126
 127 /*******************************************************************
 128  * Routine:ether_init
 129  * Description: take the Ethernet controller out of reset and wait
 130  *                 for the EEPROM load to complete.
 131  ******************************************************************/
 132 void ether_init(void)
 133 {
 134 #ifdef CONFIG_DRIVER_LAN91C96
 135         int cnt = 20;
 136
 137         __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
 138
 139         __raw_writew(0x0, LAN_RESET_REGISTER);
 140         do {
 141                 __raw_writew(0x1, LAN_RESET_REGISTER);
 142                 udelay(100);
 143                 if (cnt == 0) {
 144                         printf("1. eth reset err\n");
 145                         goto eth_reset_err_out;
 146                 }
 147                 --cnt;
 148         } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
 149
 150         cnt = 20;
 151
 152         do {
 153                 __raw_writew(0x0, LAN_RESET_REGISTER);
 154                 udelay(100);
 155                 if (cnt == 0) {
 156                         printf("2. eth reset err\n");
 157                         goto eth_reset_err_out;
 158                 }
 159                 --cnt;
 160         } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 161         udelay(1000);
 162
 163         *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01;
 164         udelay(1000);
 165
 166 eth_reset_err_out:
 167         return;
 168 #endif
 169 }
 170
 171 /**********************************************
 172  * Routine: dram_init
 173  * Description: sets uboots idea of sdram size
 174 **********************************************/
 175 int dram_init(void)
 176 {
 177         DECLARE_GLOBAL_DATA_PTR;
 178         unsigned int size0 = 0, size1 = 0;
 179         u32 mtype, btype, rev = 0, cpu = 0;
 180 #define NOT_EARLY 0
 181
 182         btype = get_board_type();
 183         mtype = get_mem_type();
 184         rev = get_cpu_rev();
 185         cpu = get_cpu_type();
 186
 187         display_board_info(btype);
 188
 189         if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 190                 printf("ddr combo\n");
 191                 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
 192         }
 193
 194         size0 = get_sdr_cs_size(SDRC_CS0_OSET);
 195         size1 = get_sdr_cs_size(SDRC_CS1_OSET);
 196
 197         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 198         gd->bd->bi_dram[0].size = size0;
 199 #if CONFIG_NR_DRAM_BANKS > 1
 200         gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
 201         gd->bd->bi_dram[1].size = size1;
 202 #endif
 203
 204         return 0;
 205 }
 206
 207 /**********************************************************
 208  * Routine: set_muxconf_regs
 209  * Description: Setting up the configuration Mux registers
 210  *              specific to the hardware
 211  *********************************************************/
 212 void set_muxconf_regs(void)
 213 {
 214         muxSetupSDRC();
 215         muxSetupGPMC();
 216         muxSetupUsb0();         /* USB Device */
 217         muxSetupUsbHost();      /* USB Host */
 218         muxSetupUART1();
 219         muxSetupLCD();
 220         muxSetupMMCSD();
 221         muxSetupTouchScreen();
 222 }
 223
 224 /*****************************************************************
 225  * Routine: peripheral_enable
 226  * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 227 ******************************************************************/
 228 void peripheral_enable(void)
 229 {
 230         unsigned int v, if_clks = 0, func_clks = 0;
 231
 232         /* Enable GP2 timer. */
 233         if_clks |= BIT4 | BIT3;
 234         func_clks |= BIT4 | BIT3;
 235         v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;   /* Sys_clk input OMAP2420_GPT2 */
 236         __raw_writel(v, CM_CLKSEL2_CORE);
 237         __raw_writel(0x1, CM_CLKSEL_WKUP);
 238
 239 #ifdef CFG_NS16550
 240         /* Enable UART1 clock */
 241         func_clks |= BIT21;
 242         if_clks |= BIT21;
 243 #endif
 244         v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;     /* Interface clocks on */
 245         __raw_writel(v, CM_ICLKEN1_CORE);
 246         v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;   /* Functional Clocks on */
 247         __raw_writel(v, CM_FCLKEN1_CORE);
 248         delay(1000);
 249
 250 #ifndef KERNEL_UPDATED
 251         {
 252 #define V1 0xffffffff
 253 #define V2 0x00000007
 254
 255                 __raw_writel(V1, CM_FCLKEN1_CORE);
 256                 __raw_writel(V2, CM_FCLKEN2_CORE);
 257                 __raw_writel(V1, CM_ICLKEN1_CORE);
 258                 __raw_writel(V1, CM_ICLKEN2_CORE);
 259         }
 260 #endif
 261 }
 262
 263 /****************************************
 264  * Routine: muxSetupUsb0 (ostboot)
 265  * Description: Setup usb muxing
 266  *****************************************/
 267 void muxSetupUsb0(void)
 268 {
 269         volatile uint8 *MuxConfigReg;
 270
 271         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
 272         *MuxConfigReg &= (uint8) (~0x1F);
 273
 274         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
 275         *MuxConfigReg &= (uint8) (~0x1F);
 276
 277         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
 278         *MuxConfigReg &= (uint8) (~0x1F);
 279
 280         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
 281         *MuxConfigReg &= (uint8) (~0x1F);
 282
 283         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
 284         *MuxConfigReg &= (uint8) (~0x1F);
 285
 286         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
 287         *MuxConfigReg &= (uint8) (~0x1F);
 288
 289         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
 290         *MuxConfigReg &= (uint8) (~0x1F);
 291 }
 292
 293 #define CONTROL_PADCONF_USB1_RCV        ((volatile uint8 *)0x480000EB)
 294 #define CONTROL_PADCONF_USB1_TXEN       ((volatile uint8 *)0x480000EC)
 295 #define CONTROL_PADCONF_GPIO69          ((volatile uint8 *)0x480000ED)
 296 #define CONTROL_PADCONF_GPIO70          ((volatile uint8 *)0x480000EE)
 297
 298 #define CONTROL_PADCONF_GPIO102         ((volatile uint8 *)0x48000116)
 299 #define CONTROL_PADCONF_GPIO103         ((volatile uint8 *)0x48000117)
 300 #define CONTROL_PADCONF_GPIO104         ((volatile uint8 *)0x48000118)
 301 #define CONTROL_PADCONF_GPIO105         ((volatile uint8 *)0x48000119)
 302 /****************************************
 303  * Routine: muxSetupUSBHost (ostboot)
 304  * Description: Setup USB Host muxing
 305  *****************************************/
 306 void muxSetupUsbHost(void)
 307 {
 308         volatile uint8 *MuxConfigReg;
 309
 310         /* V19 */
 311         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_RCV;
 312         *MuxConfigReg = 1;
 313         /* W20 */
 314         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_TXEN;
 315         *MuxConfigReg = 1;
 316         /* N14 */
 317         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO69;
 318         *MuxConfigReg = 3;
 319         /* P15 */
 320         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO70;
 321         *MuxConfigReg = 3;
 322
 323         /* L18 */
 324         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO102;
 325         *MuxConfigReg = 3;
 326         /* L19 */
 327         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO103;
 328         *MuxConfigReg = 3;
 329         /* K15 */
 330         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO104;
 331         *MuxConfigReg = 3;
 332         /* K14 */
 333         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO105;
 334         *MuxConfigReg = 3;
 335 }
 336
 337 /****************************************
 338  * Routine: muxSetupUART1 (ostboot)
 339  * Description: Set up uart1 muxing
 340  *****************************************/
 341 void muxSetupUART1(void)
 342 {
 343         volatile unsigned char *MuxConfigReg;
 344
 345         /* UART1_CTS pin configuration, PIN = D21 */
 346         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
 347         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 348
 349         /* UART1_RTS pin configuration, PIN = H21 */
 350         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
 351         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 352
 353         /* UART1_TX pin configuration, PIN = L20 */
 354         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
 355         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 356
 357         /* UART1_RX pin configuration, PIN = T21 */
 358         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
 359         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 360 }
 361
 362 /****************************************
 363  * Routine: muxSetupLCD (ostboot)
 364  * Description: Setup lcd muxing
 365  *****************************************/
 366 void muxSetupLCD(void)
 367 {
 368         volatile unsigned char *MuxConfigReg;
 369
 370         /* LCD_D0 pin configuration, PIN = Y7 */
 371         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
 372         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 373
 374         /* LCD_D1 pin configuration, PIN = P10 */
 375         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
 376         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 377
 378         /* LCD_D2 pin configuration, PIN = V8 */
 379         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
 380         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 381
 382         /* LCD_D3 pin configuration, PIN = Y8 */
 383         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
 384         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 385
 386         /* LCD_D4 pin configuration, PIN = W8 */
 387         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
 388         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 389
 390         /* LCD_D5 pin configuration, PIN = R10 */
 391         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
 392         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 393
 394         /* LCD_D6 pin configuration, PIN = Y9 */
 395         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
 396         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 397
 398         /* LCD_D7 pin configuration, PIN = V9 */
 399         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
 400         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 401
 402         /* LCD_D8 pin configuration, PIN = W9 */
 403         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
 404         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 405
 406         /* LCD_D9 pin configuration, PIN = P11 */
 407         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
 408         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 409
 410         /* LCD_D10 pin configuration, PIN = V10 */
 411         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
 412         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 413
 414         /* LCD_D11 pin configuration, PIN = Y10 */
 415         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
 416         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 417
 418         /* LCD_D12 pin configuration, PIN = W10 */
 419         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
 420         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 421
 422         /* LCD_D13 pin configuration, PIN = R11 */
 423         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
 424         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 425
 426         /* LCD_D14 pin configuration, PIN = V11 */
 427         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
 428         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 429
 430         /* LCD_D15 pin configuration, PIN = W11 */
 431         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
 432         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 433
 434         /* LCD_D16 pin configuration, PIN = P12 */
 435         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
 436         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 437
 438         /* LCD_D17 pin configuration, PIN = R12 */
 439         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
 440         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 441
 442         /* LCD_PCLK pin configuration, PIN = W6 */
 443         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
 444         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 445
 446         /* LCD_VSYNC pin configuration, PIN = V7 */
 447         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
 448         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 449
 450         /* LCD_HSYNC pin configuration, PIN = Y6 */
 451         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
 452         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 453
 454         /* LCD_ACBIAS pin configuration, PIN = W7 */
 455         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
 456         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 457 }
 458
 459 /****************************************
 460  * Routine: muxSetupMMCSD (ostboot)
 461  * Description: set up MMC muxing
 462  *****************************************/
 463 void muxSetupMMCSD(void)
 464 {
 465         volatile unsigned char *MuxConfigReg;
 466
 467         /* SDMMC_CLKI pin configuration, PIN = H15 */
 468         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI;
 469         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 470
 471         /* SDMMC_CLKO pin configuration, PIN = G19 */
 472         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO;
 473         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 474
 475         /* SDMMC_CMD pin configuration, PIN = H18 */
 476         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD;
 477         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 478         /* External pull-ups are present. */
 479         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 480
 481         /* SDMMC_DAT0 pin configuration, PIN = F20 */
 482         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0;
 483         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 484         /* External pull-ups are present. */
 485         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 486
 487         /* SDMMC_DAT1 pin configuration, PIN = H14 */
 488         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1;
 489         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 490         /* External pull-ups are present. */
 491         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 492
 493         /* SDMMC_DAT2 pin configuration, PIN = E19 */
 494         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2;
 495         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 496         /* External pull-ups are present. */
 497         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 498
 499         /* SDMMC_DAT3 pin configuration, PIN = D19 */
 500         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3;
 501         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 502         /* External pull-ups are present. */
 503         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 504
 505         /* SDMMC_DDIR0 pin configuration, PIN = F19 */
 506         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0;
 507         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 508
 509         /* SDMMC_DDIR1 pin configuration, PIN = E20 */
 510         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1;
 511         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 512
 513         /* SDMMC_DDIR2 pin configuration, PIN = F18 */
 514         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2;
 515         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 516
 517         /* SDMMC_DDIR3 pin configuration, PIN = E18 */
 518         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3;
 519         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 520
 521         /* SDMMC_CDIR pin configuration, PIN = G18 */
 522         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR;
 523         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 524 }
 525
 526 /******************************************
 527  * Routine: muxSetupTouchScreen (ostboot)
 528  * Description: Set up touch screen muxing
 529 *******************************************/
 530 void muxSetupTouchScreen(void)
 531 {
 532         volatile unsigned char *MuxConfigReg;
 533
 534         /* SPI1_CLK pin configuration, PIN = U18 */
 535         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK;
 536         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 537
 538         /* SPI1_MOSI pin configuration, PIN = V20 */
 539         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO;
 540         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 541
 542         /* SPI1_MISO pin configuration, PIN = T18 */
 543         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI;
 544         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 545
 546         /* SPI1_nCS0 pin configuration, PIN = U19 */
 547         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0;
 548         *MuxConfigReg = 0x00;   /* Mode = 0, PUPD=Disabled */
 549
 550 #define CONTROL_PADCONF_GPIO85  CONTROL_PADCONF_SPI1_NCS1
 551
 552         /* PEN_IRQ pin configuration, PIN = N15 */
 553         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_GPIO85;
 554         *MuxConfigReg = 0x03;   /* Mode = 3, PUPD=Disabled */
 555 }
 556
 557 /***************************************************************
 558  * Routine: muxSetupGPMC (ostboot)
 559  * Description: Configures balls which cam up in protected mode
 560 ***************************************************************/
 561 void muxSetupGPMC(void)
 562 {
 563         volatile uint8 *MuxConfigReg;
 564         volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
 565
 566         /* gpmc_io_dir */
 567         *MCR = 0x19000000;
 568
 569         /* NOR FLASH CS0 */
 570         /* signal - Gpmc_clk;
 571                 pin - J4; offset - 0x0088; mode - 0; Byte-3  Pull/up - N/A */
 572         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3;
 573         *MuxConfigReg = 0x00;
 574
 575         /* MPDB(Multi Port Debug Port) CS1 */
 576         /* signal - gpmc_ncs1;
 577                 pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
 578         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1;
 579         *MuxConfigReg = 0x00;
 580
 581         /* signal - Gpmc_ncs2;
 582                 pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
 583         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2;
 584         *MuxConfigReg = 0x00;
 585
 586         /* signal - Gpmc_ncs3;
 587                 pin - N2; offset - 0x008C; mode - 0; Byte-3 Pull/up - N/A */
 588         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3;
 589         *MuxConfigReg = 0x00;
 590
 591         MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000090);
 592         *MuxConfigReg = 0x00;
 593         MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000091);
 594         *MuxConfigReg = 0x00;
 595         MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000092);
 596         *MuxConfigReg = 0x00;
 597         MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000093);
 598         *MuxConfigReg = 0x00;
 599 }
 600
 601 /****************************************************************
 602  * Routine: muxSetupSDRC (ostboot)
 603  * Description: Configures balls which come up in protected mode
 604 ****************************************************************/
 605 void muxSetupSDRC(void)
 606 {
 607         /* It's set by IPL */
 608 }