2 * (C) Copyright 2005-2007
4 * Kyungmin Park <kyungmin.park@samsung.com>
6 * Derived from omap2420
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/omap2420.h>
27 #include <asm/arch/bits.h>
28 #include <asm/arch/mux.h>
29 #include <asm/arch/mem.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/sys_info.h>
36 /************************************************************
37 * sdelay() - simple spin loop. Will be constant time as
38 * its generally used in 12MHz bypass conditions only. This
39 * is necessary until timers are accessible.
41 * not inline to increase chances its in cache when called
42 *************************************************************/
43 void sdelay(unsigned long loops)
45 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
46 "bne 1b":"=r" (loops):"0"(loops));
49 /*****************************************************************************
50 * prcm_init() - inits clocks for PRCM as defined in clocks.h
51 * (config II default). Called from SRAM, or Flash (using temp SRAM stack).
52 *****************************************************************************/
57 /**************************************************************************
58 * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
59 * command line mem=xyz use all memory with out discontigious support
60 * compiled in. Could do it at the ATAG, but there really is two banks...
61 * Called as part of 2nd phase DDR init.
62 **************************************************************************/
63 void make_cs1_contiguous(void)
65 u32 size, a_add_low, a_add_high;
67 size = get_sdr_cs_size(SDRC_CS0_OSET);
68 size /= SZ_32M; /* find size to offset CS1 */
69 a_add_high = (size & 3) << 8; /* set up low field */
70 a_add_low = (size & 0x3C) >> 2; /* set up high field */
71 __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
74 /********************************************************
75 * mem_ok() - test used to see if timings are correct
76 * for a part. Helps in gussing which part
77 * we are currently using.
78 *******************************************************/
82 u32 pattern = 0x12345678;
84 __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400); /* clear pos A */
85 __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */
86 __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4); /* remove pattern off the bus */
87 val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400); /* get pos A value */
88 val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
90 if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed */
96 /********************************************************
97 * sdrc_init() - init the sdrc chip selects CS0 and CS1
98 * - early init routines, called from flash or
100 *******************************************************/
104 /* only init up first bank here */
105 do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
108 /*************************************************************************
109 * do_sdrc_init(): initialize the SDRAM for use.
110 * -called from low level code with stack only.
111 * -code sets up SDRAM timing and muxing for 2422 or 2420.
112 * -optimal settings can be placed here, or redone after i2c
113 * inspection of board info
115 * This is a bit ugly, but should handle all memory moduels
116 * used with the APOLLON. The first time though this code from s_init()
117 * we configure the first chip select. Later on we come back and
118 * will configure the 2nd chip select if it exists.
120 **************************************************************************/
121 void do_sdrc_init(u32 offset, u32 early)
125 /*****************************************************
126 * gpmc_init(): init gpmc bus
127 * Init GPMC for x16, MuxMode (SDRAM in x32).
128 * This code can only be executed from SRAM or SDRAM.
129 *****************************************************/
132 u32 mux = 0, mtype, mwidth, rev, tval;
135 if (rev == CPU_2420_2422_ES1)
138 tval = 0; /* disable bit switched meaning */
140 /* global settings */
141 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
142 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
143 __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
145 __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
147 __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */
150 /* discover bus connection from sysboot */
151 if (is_gpmc_muxed() == GPMC_MUXED)
153 mtype = get_gpmc0_type();
154 mwidth = get_gpmc0_width();
157 __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
161 __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
162 __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
163 __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
164 __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
165 __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
166 __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
167 __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0); #else
168 __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
170 __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
171 __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
172 __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
173 __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
174 __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
175 /* enable new mapping */
176 __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
181 __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
184 __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
185 __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
186 __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
187 __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
188 __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
189 __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
190 __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
194 __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
196 /* It's same as cs 0 */
197 __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
198 __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
199 __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
200 __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
201 __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
203 __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
205 __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
210 __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
213 __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
214 __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
215 __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
216 __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
217 __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
218 __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
219 __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
223 __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
224 __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
225 __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));