4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/pxa.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 void balloon3_init_fpga(void);
35 * Miscelaneous platform dependent initialisations
40 /* We have RAM, disable cache */
44 /* arch number of vpac270 */
45 gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
47 /* adress of boot parameters */
48 gd->bd->bi_boot_params = 0xa0000100;
59 gd->ram_size = PHYS_SDRAM_1_SIZE;
63 void dram_init_banksize(void)
65 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
66 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
67 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
69 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
70 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
71 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
75 int usb_board_init(void)
77 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
78 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
81 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
83 while (readl(UHCHR) & UHCHR_FSBIR)
86 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
87 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
89 /* Clear any OTG Pin Hold */
90 if (readl(PSSR) & PSSR_OTGPH)
91 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
93 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
94 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
96 /* Set port power control mask bits, only 3 ports. */
97 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
100 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
101 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
106 void usb_board_init_fail(void)
111 void usb_board_stop(void)
113 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
115 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
117 writel(readl(UHCCOMS) | 1, UHCCOMS);
120 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
126 #if defined(CONFIG_FPGA)
127 /* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
128 int fpga_pgm_fn(int nassert, int nflush, int cookie)
135 writel(0x100, GPCR3);
137 writel(0x100, GPSR3);
141 /* Check GPIO83 -- INITB */
142 int fpga_init_fn(int cookie)
144 return !(readl(GPLR2) & 0x80000);
147 /* Check GPIO84 -- BUSY */
148 int fpga_busy_fn(int cookie)
150 return !(readl(GPLR2) & 0x100000);
153 /* Check GPIO111 -- DONE */
154 int fpga_done_fn(int cookie)
156 return readl(GPLR3) & 0x8000;
159 /* Configure GPIO104 as GPIO and deassert it */
160 int fpga_pre_config_fn(int cookie)
162 writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
163 writel(0x100, GPCR3);
167 /* Configure GPIO104 as nSKTSEL */
168 int fpga_post_config_fn(int cookie)
170 writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
175 int fpga_wr_fn(int nassert_write, int flush, int cookie)
180 writel(0x100, GPCR3);
182 writel(0x100, GPSR3);
184 return nassert_write;
187 /* Write program to the FPGA */
188 int fpga_wdata_fn(uchar data, int flush, int cookie)
190 writeb(data, 0x10f00000);
194 /* Toggle Clock pin -- NO-OP */
195 int fpga_clk_fn(int assert_clk, int flush, int cookie)
200 /* Toggle ChipSelect pin -- NO-OP */
201 int fpga_cs_fn(int assert_clk, int flush, int cookie)
206 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
222 Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
223 (void *)&balloon3_fpga_fns, 0);
225 /* Initialize the FPGA */
226 void balloon3_init_fpga(void)
229 fpga_add(fpga_xilinx, &fpga);
232 void balloon3_init_fpga(void) {}
233 #endif /* CONFIG_FPGA */