2 * Board functions for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <fsl_esdhc.h>
15 #include <fdt_support.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/imx-common/mxc_i2c.h>
21 #include <asm/imx-common/sata.h>
25 #include "../common/eeprom.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #ifdef CONFIG_DWC_AHSATA
30 static int cm_fx6_issd_gpios[] = {
31 /* The order of the GPIOs in the array is important! */
35 CM_FX6_SATA_NSTANDBY1,
36 CM_FX6_SATA_NSTANDBY2,
40 static void cm_fx6_sata_power(int on)
44 if (!on) { /* tell the iSSD that the power will be removed */
45 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
49 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
50 gpio_direction_output(cm_fx6_issd_gpios[i], on);
54 if (!on) /* for compatibility lower the power loss interrupt */
55 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
58 static iomux_v3_cfg_t const sata_pads[] = {
60 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
61 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
62 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
63 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
65 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
66 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
67 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
68 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
69 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
72 static int cm_fx6_setup_issd(void)
76 SETUP_IOMUX_PADS(sata_pads);
78 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
79 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
84 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
91 #define CM_FX6_SATA_INIT_RETRIES 10
92 int sata_initialize(void)
96 /* Make sure this gpio has logical 0 value */
97 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
100 cm_fx6_sata_power(0);
102 cm_fx6_sata_power(1);
104 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
107 printf("SATA setup failed: %d\n", err);
113 err = __sata_initialize();
117 /* There is no device on the SATA port */
118 if (sata_port_status(0, 0) == 0)
121 /* There's a device, but link not established. Retry */
127 static int cm_fx6_setup_issd(void) { return 0; }
130 #ifdef CONFIG_SYS_I2C_MXC
131 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
132 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
133 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
136 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
137 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
139 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
140 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
144 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
145 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
147 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
148 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
152 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
153 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
155 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
156 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
160 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
164 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
166 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
171 static int cm_fx6_setup_i2c(void)
175 /* i2c<x>_pads are wierd macro variables; we can't use an array */
176 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
179 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
182 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
189 static int cm_fx6_setup_i2c(void) { return 0; }
192 #ifdef CONFIG_USB_EHCI_MX6
193 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
194 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
195 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
196 #define MX6_USBNC_BASEADDR 0x2184800
197 #define USBNC_USB_H1_PWR_POL (1 << 9)
199 static int cm_fx6_setup_usb_host(void)
203 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
207 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
208 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
213 static int cm_fx6_setup_usb_otg(void)
216 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
218 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
220 printf("USB OTG pwr gpio request failed: %d\n", err);
224 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
225 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
226 MUX_PAD_CTRL(WEAK_PULLDOWN));
227 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
228 /* disable ext. charger detect, or it'll affect signal quality at dp. */
229 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
232 int board_ehci_hcd_init(int port)
235 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
237 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
241 /* Set PWR polarity to match power switch's enable polarity */
242 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
243 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
248 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
257 int board_ehci_power(int port, int on)
260 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
265 static int cm_fx6_setup_usb_otg(void) { return 0; }
266 static int cm_fx6_setup_usb_host(void) { return 0; }
269 #ifdef CONFIG_FEC_MXC
270 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
271 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
273 static int mx6_rgmii_rework(struct phy_device *phydev)
277 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
278 * which cause ethernet link down/up issue, so disable SmartEEE
280 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
281 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
282 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
283 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
285 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
287 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
288 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
289 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
290 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
292 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
295 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
297 /* introduce tx clock delay */
298 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
299 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
301 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
306 int board_phy_config(struct phy_device *phydev)
308 mx6_rgmii_rework(phydev);
310 if (phydev->drv->config)
311 return phydev->drv->config(phydev);
316 static iomux_v3_cfg_t const enet_pads[] = {
317 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
318 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
319 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
320 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
321 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
322 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
323 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
324 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
325 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
326 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
327 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
328 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
329 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
330 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
331 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
332 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
333 MUX_PAD_CTRL(ENET_PAD_CTRL)),
334 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
335 MUX_PAD_CTRL(ENET_PAD_CTRL)),
336 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
337 MUX_PAD_CTRL(ENET_PAD_CTRL)),
340 static int handle_mac_address(void)
342 unsigned char enetaddr[6];
345 rc = eth_getenv_enetaddr("ethaddr", enetaddr);
349 rc = cl_eeprom_read_mac_addr(enetaddr);
353 if (!is_valid_ether_addr(enetaddr))
356 return eth_setenv_enetaddr("ethaddr", enetaddr);
359 int board_eth_init(bd_t *bis)
363 err = handle_mac_address();
365 puts("No MAC address found\n");
367 SETUP_IOMUX_PADS(enet_pads);
369 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
371 printf("Etnernet NRST gpio request failed: %d\n", err);
372 gpio_direction_output(CM_FX6_ENET_NRST, 0);
374 gpio_set_value(CM_FX6_ENET_NRST, 1);
376 return cpu_eth_init(bis);
380 #ifdef CONFIG_NAND_MXS
381 static iomux_v3_cfg_t const nand_pads[] = {
382 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
383 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
384 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
385 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
386 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
387 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
388 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
389 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
390 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
391 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
392 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
393 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
394 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
395 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
398 static void cm_fx6_setup_gpmi_nand(void)
400 SETUP_IOMUX_PADS(nand_pads);
401 /* Enable clock roots */
402 enable_usdhc_clk(1, 3);
403 enable_usdhc_clk(1, 4);
405 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
406 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
407 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
410 static void cm_fx6_setup_gpmi_nand(void) {}
413 #ifdef CONFIG_FSL_ESDHC
414 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
420 static enum mxc_clock usdhc_clk[3] = {
426 int board_mmc_init(bd_t *bis)
430 cm_fx6_set_usdhc_iomux();
431 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
432 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
433 usdhc_cfg[i].max_bus_width = 4;
434 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
435 enable_usdhc_clk(1, i);
442 #ifdef CONFIG_MXC_SPI
443 int cm_fx6_setup_ecspi(void)
445 cm_fx6_set_ecspi_iomux();
446 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
449 int cm_fx6_setup_ecspi(void) { return 0; }
452 #ifdef CONFIG_OF_BOARD_SETUP
453 void ft_board_setup(void *blob, bd_t *bd)
458 if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
459 fdt_find_and_setprop(blob, "/fec", "local-mac-address",
469 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
470 cm_fx6_setup_gpmi_nand();
472 ret = cm_fx6_setup_ecspi();
474 printf("Warning: ECSPI setup failed: %d\n", ret);
476 ret = cm_fx6_setup_usb_otg();
478 printf("Warning: USB OTG setup failed: %d\n", ret);
480 ret = cm_fx6_setup_usb_host();
482 printf("Warning: USB host setup failed: %d\n", ret);
485 * cm-fx6 may have iSSD not assembled and in this case it has
486 * bypasses for a (m)SATA socket on the baseboard. The socketed
487 * device is not controlled by those GPIOs. So just print a warning
488 * if the setup fails.
490 ret = cm_fx6_setup_issd();
492 printf("Warning: iSSD setup failed: %d\n", ret);
494 /* Warn on failure but do not abort boot */
495 ret = cm_fx6_setup_i2c();
497 printf("Warning: I2C setup failed: %d\n", ret);
504 puts("Board: CM-FX6\n");
508 void dram_init_banksize(void)
510 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
511 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
513 switch (gd->ram_size) {
514 case 0x10000000: /* DDR_16BIT_256MB */
515 gd->bd->bi_dram[0].size = 0x10000000;
516 gd->bd->bi_dram[1].size = 0;
518 case 0x20000000: /* DDR_32BIT_512MB */
519 gd->bd->bi_dram[0].size = 0x20000000;
520 gd->bd->bi_dram[1].size = 0;
523 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
524 gd->bd->bi_dram[0].size = 0x20000000;
525 gd->bd->bi_dram[1].size = 0x20000000;
526 } else { /* DDR_64BIT_1GB */
527 gd->bd->bi_dram[0].size = 0x40000000;
528 gd->bd->bi_dram[1].size = 0;
531 case 0x80000000: /* DDR_64BIT_2GB */
532 gd->bd->bi_dram[0].size = 0x40000000;
533 gd->bd->bi_dram[1].size = 0x40000000;
535 case 0xEFF00000: /* DDR_64BIT_4GB */
536 gd->bd->bi_dram[0].size = 0x70000000;
537 gd->bd->bi_dram[1].size = 0x7FF00000;
544 gd->ram_size = imx_ddr_size();
545 switch (gd->ram_size) {
552 gd->ram_size -= 0x100000;
555 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
562 u32 get_board_rev(void)
564 return cl_eeprom_get_board_rev();