2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on da830evm.c. Original Copyrights follow:
6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <spi_flash.h>
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/emif_defs.h>
32 #include <asm/arch/emac_defs.h>
33 #include <asm/arch/pinmux_defs.h>
35 #include <asm/arch/davinci_misc.h>
36 #include <asm/errno.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #ifdef CONFIG_DRIVER_TI_EMAC
42 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
47 #endif /* CONFIG_DRIVER_TI_EMAC */
49 #define CFG_MAC_ADDR_SPI_BUS 0
50 #define CFG_MAC_ADDR_SPI_CS 0
51 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
52 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
54 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
56 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
57 static int get_mac_addr(u8 *addr)
59 struct spi_flash *flash;
62 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
63 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
65 printf("Error - unable to probe SPI flash.\n");
69 ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr);
71 printf("Error - unable to read MAC address from SPI flash.\n");
79 void dsp_lpsc_on(unsigned domain, unsigned int id)
81 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
82 struct davinci_psc_regs *psc_regs;
84 psc_regs = davinci_psc0_regs;
85 mdstat = &psc_regs->psc0.mdstat[id];
86 mdctl = &psc_regs->psc0.mdctl[id];
87 ptstat = &psc_regs->ptstat;
88 ptcmd = &psc_regs->ptcmd;
90 while (*ptstat & (0x1 << domain))
93 if ((*mdstat & 0x1f) == 0x03)
94 return; /* Already on and enabled */
98 *ptcmd = 0x1 << domain;
100 while (*ptstat & (0x1 << domain))
102 while ((*mdstat & 0x1f) != 0x03)
103 ; /* Probably an overkill... */
106 static void dspwake(void)
108 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
111 /* if the device is ARM only, return */
112 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
115 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
118 *resetvect++ = 0x1E000; /* DSP Idle */
119 /* clear out the next 10 words as NOP */
120 memset(resetvect, 0, sizeof(unsigned) *10);
122 /* setup the DSP reset vector */
123 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
125 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
126 val = readl(PSC0_MDCTL + (15 * 4));
128 writel(val, (PSC0_MDCTL + (15 * 4)));
131 int misc_init_r(void)
135 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
136 uchar env_enetaddr[6];
141 enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);
142 spi_mac_read = get_mac_addr(buff);
145 * MAC address not present in the environment
146 * try and read the MAC address from SPI flash
149 if (!enetaddr_found) {
151 if (is_valid_ether_addr(buff)) {
152 if (eth_setenv_enetaddr("ethaddr", buff)) {
153 printf("Warning: Failed to "
154 "set MAC address from SPI flash\n");
157 printf("Warning: Invalid "
158 "MAC address read from SPI flash\n");
163 * MAC address present in environment compare it with
164 * the MAC address in SPI flash and warn on mismatch
166 if (!spi_mac_read && is_valid_ether_addr(buff) &&
167 memcmp(env_enetaddr, buff, 6))
168 printf("Warning: MAC address in SPI flash don't match "
169 "with the MAC address in the environment\n");
170 printf("Default using MAC address from environment\n");
176 static const struct pinmux_config gpio_pins[] = {
177 #ifdef CONFIG_USE_NOR
178 /* GP0[11] is required for NOR to work on Rev 3 EVMs */
179 { pinmux(0), 8, 4 }, /* GP0[11] */
183 const struct pinmux_resource pinmuxes[] = {
184 #ifdef CONFIG_DRIVER_TI_EMAC
185 PINMUX_ITEM(emac_pins_mdio),
186 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
187 PINMUX_ITEM(emac_pins_rmii),
189 PINMUX_ITEM(emac_pins_mii),
192 #ifdef CONFIG_SPI_FLASH
193 PINMUX_ITEM(spi1_pins_base),
194 PINMUX_ITEM(spi1_pins_scs0),
196 PINMUX_ITEM(uart2_pins_txrx),
197 PINMUX_ITEM(uart2_pins_rtscts),
198 PINMUX_ITEM(i2c0_pins),
199 #ifdef CONFIG_NAND_DAVINCI
200 PINMUX_ITEM(emifa_pins_cs3),
201 PINMUX_ITEM(emifa_pins_cs4),
202 PINMUX_ITEM(emifa_pins_nand),
203 #elif defined(CONFIG_USE_NOR)
204 PINMUX_ITEM(emifa_pins_cs2),
205 PINMUX_ITEM(emifa_pins_nor),
207 PINMUX_ITEM(gpio_pins),
210 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
212 const struct lpsc_resource lpsc[] = {
213 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
214 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
215 { DAVINCI_LPSC_EMAC }, /* image download */
216 { DAVINCI_LPSC_UART2 }, /* console */
217 { DAVINCI_LPSC_GPIO },
220 const int lpsc_size = ARRAY_SIZE(lpsc);
222 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
223 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
226 #define REV_AM18X_EVM 0x100
229 * get_board_rev() - setup to pass kernel board revision information
231 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
237 u32 get_board_rev(void)
240 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
243 s = getenv("maxcpuclk");
245 maxcpuclk = simple_strtoul(s, NULL, 10);
247 if (maxcpuclk >= 456000000)
249 else if (maxcpuclk >= 408000000)
251 else if (maxcpuclk >= 372000000)
253 #ifdef CONFIG_DA850_AM18X_EVM
254 rev |= REV_AM18X_EVM;
259 int board_early_init_f(void)
262 * Power on required peripherals
263 * ARM does not have access by default to PSC0 and PSC1
264 * assuming here that the DSP bootloader has set the IOPU
265 * such that PSC access is available to ARM
267 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
275 #ifdef CONFIG_USE_NOR
279 #ifndef CONFIG_USE_IRQ
283 #ifdef CONFIG_NAND_DAVINCI
285 * NAND CS setup - cycle counts based on da850evm NAND timings in the
286 * Linux kernel @ 25MHz EMIFA
288 writel((DAVINCI_ABCR_WSETUP(0) |
289 DAVINCI_ABCR_WSTROBE(1) |
290 DAVINCI_ABCR_WHOLD(0) |
291 DAVINCI_ABCR_RSETUP(0) |
292 DAVINCI_ABCR_RSTROBE(1) |
293 DAVINCI_ABCR_RHOLD(0) |
295 DAVINCI_ABCR_ASIZE_8BIT),
296 &davinci_emif_regs->ab2cr); /* CS3 */
299 /* arch number of the board */
300 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
302 /* address of boot parameters */
303 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
305 /* setup the SUSPSRC for ARM to control emulation suspend */
306 writel(readl(&davinci_syscfg_regs->suspsrc) &
307 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
308 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
309 DAVINCI_SYSCFG_SUSPSRC_UART2),
310 &davinci_syscfg_regs->suspsrc);
312 /* configure pinmux settings */
313 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
316 #ifdef CONFIG_USE_NOR
317 /* Set the GPIO direction as output */
318 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
320 /* Set the output as low */
321 val = readl(GPIO_BANK0_REG_SET_ADDR);
323 writel(val, GPIO_BANK0_REG_CLR_ADDR);
326 #ifdef CONFIG_DRIVER_TI_EMAC
327 davinci_emac_mii_mode_sel(HAS_RMII);
328 #endif /* CONFIG_DRIVER_TI_EMAC */
330 /* enable the console UART */
331 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
332 DAVINCI_UART_PWREMU_MGMT_UTRST),
333 &davinci_uart2_ctrl_regs->pwremu_mgmt);
338 #ifdef CONFIG_DRIVER_TI_EMAC
340 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
344 * DA850/OMAP-L138 EVM can interface to a daughter card for
345 * additional features. This card has an I2C GPIO Expander TCA6416
346 * to select the required functions like camera, RMII Ethernet,
347 * character LCD, video.
349 * Initialization of the expander involves configuring the
350 * polarity and direction of the ports. P07-P05 are used here.
351 * These ports are connected to a Mux chip which enables only one
352 * functionality at a time.
354 * For RMII phy to respond, the MII MDIO clock has to be disabled
355 * since both the PHY devices have address as zero. The MII MDIO
356 * clock is controlled via GPIO2[6].
358 * This code is valid for Beta version of the hardware
360 int rmii_hw_init(void)
362 const struct pinmux_config gpio_pins[] = {
369 /* PinMux for GPIO */
370 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
373 /* I2C Exapnder configuration */
374 /* Set polarity to non-inverted */
377 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
379 printf("\nExpander @ 0x%02x write FAILED!!!\n",
380 CONFIG_SYS_I2C_EXPANDER_ADDR);
384 /* Configure P07-P05 as outputs */
387 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
389 printf("\nExpander @ 0x%02x write FAILED!!!\n",
390 CONFIG_SYS_I2C_EXPANDER_ADDR);
393 /* For Ethernet RMII selection
398 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
399 printf("\nExpander @ 0x%02x read FAILED!!!\n",
400 CONFIG_SYS_I2C_EXPANDER_ADDR);
404 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
405 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
406 printf("\nExpander @ 0x%02x write FAILED!!!\n",
407 CONFIG_SYS_I2C_EXPANDER_ADDR);
410 /* Set the output as high */
411 temp = REG(GPIO_BANK2_REG_SET_ADDR);
413 REG(GPIO_BANK2_REG_SET_ADDR) = temp;
415 /* Set the GPIO direction as output */
416 temp = REG(GPIO_BANK2_REG_DIR_ADDR);
417 temp &= ~(0x01 << 6);
418 REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
422 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
425 * Initializes on-board ethernet controllers.
427 int board_eth_init(bd_t *bis)
429 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
430 /* Select RMII fucntion through the expander */
432 printf("RMII hardware init failed!!!\n");
434 if (!davinci_emac_initialize()) {
435 printf("Error: Ethernet init failed!\n");
441 #endif /* CONFIG_DRIVER_TI_EMAC */