board/davinci/schmoogie/dv_board.c

   1 /*
   2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   3  *
   4  * Parts are shamelessly stolen from various TI sources, original copyright
   5  * follows:
   6  * -----------------------------------------------------------------
   7  *
   8  * Copyright (C) 2004 Texas Instruments.
   9  *
  10  * ----------------------------------------------------------------------------
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  * ----------------------------------------------------------------------------
  25  */
  26
  27 #include <common.h>
  28 #include <i2c.h>
  29 #include <asm/arch/hardware.h>
  30 #include <asm/arch/emac_defs.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 extern void     timer_init(void);
  35 extern int      eth_hw_init(void);
  36 extern phy_t    phy;
  37
  38
  39 /* Works on Always On power domain only (no PD argument) */
  40 void lpsc_on(unsigned int id)
  41 {
  42         dv_reg_p        mdstat, mdctl;
  43
  44         if (id >= DAVINCI_LPSC_GEM)
  45                 return;                 /* Don't work on DSP Power Domain */
  46
  47         mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
  48         mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
  49
  50         while (REG(PSC_PTSTAT) & 0x01) {;}
  51
  52         if ((*mdstat & 0x1f) == 0x03)
  53                 return;                 /* Already on and enabled */
  54
  55         *mdctl |= 0x03;
  56
  57         /* Special treatment for some modules as for sprue14 p.7.4.2 */
  58         if (    (id == DAVINCI_LPSC_VPSSSLV) ||
  59                 (id == DAVINCI_LPSC_EMAC) ||
  60                 (id == DAVINCI_LPSC_EMAC_WRAPPER) ||
  61                 (id == DAVINCI_LPSC_MDIO) ||
  62                 (id == DAVINCI_LPSC_USB) ||
  63                 (id == DAVINCI_LPSC_ATA) ||
  64                 (id == DAVINCI_LPSC_VLYNQ) ||
  65                 (id == DAVINCI_LPSC_UHPI) ||
  66                 (id == DAVINCI_LPSC_DDR_EMIF) ||
  67                 (id == DAVINCI_LPSC_AEMIF) ||
  68                 (id == DAVINCI_LPSC_MMC_SD) ||
  69                 (id == DAVINCI_LPSC_MEMSTICK) ||
  70                 (id == DAVINCI_LPSC_McBSP) ||
  71                 (id == DAVINCI_LPSC_GPIO)
  72            )
  73                 *mdctl |= 0x200;
  74
  75         REG(PSC_PTCMD) = 0x01;
  76
  77         while (REG(PSC_PTSTAT) & 0x03) {;}
  78         while ((*mdstat & 0x1f) != 0x03) {;}    /* Probably an overkill... */
  79 }
  80
  81 void dsp_on(void)
  82 {
  83         int     i;
  84
  85         if (REG(PSC_PDSTAT1) & 0x1f)
  86                 return;                 /* Already on */
  87
  88         REG(PSC_GBLCTL) |= 0x01;
  89         REG(PSC_PDCTL1) |= 0x01;
  90         REG(PSC_PDCTL1) &= ~0x100;
  91         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
  92         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
  93         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
  94         REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
  95         REG(PSC_PTCMD) = 0x02;
  96
  97         for (i = 0; i < 100; i++) {
  98                 if (REG(PSC_EPCPR) & 0x02)
  99                         break;
 100         }
 101
 102         REG(PSC_CHP_SHRTSW) = 0x01;
 103         REG(PSC_PDCTL1) |= 0x100;
 104         REG(PSC_EPCCR) = 0x02;
 105
 106         for (i = 0; i < 100; i++) {
 107                 if (!(REG(PSC_PTSTAT) & 0x02))
 108                         break;
 109         }
 110
 111         REG(PSC_GBLCTL) &= ~0x1f;
 112 }
 113
 114
 115 int board_init(void)
 116 {
 117         /* arch number of the board */
 118         gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
 119
 120         /* address of boot parameters */
 121         gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
 122
 123         /* Workaround for TMS320DM6446 errata 1.3.22 */
 124         REG(PSC_SILVER_BULLET) = 0;
 125
 126         /* Power on required peripherals */
 127         lpsc_on(DAVINCI_LPSC_EMAC);
 128         lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
 129         lpsc_on(DAVINCI_LPSC_MDIO);
 130         lpsc_on(DAVINCI_LPSC_I2C);
 131         lpsc_on(DAVINCI_LPSC_UART0);
 132         lpsc_on(DAVINCI_LPSC_TIMER1);
 133         lpsc_on(DAVINCI_LPSC_GPIO);
 134
 135         /* Powerup the DSP */
 136         dsp_on();
 137
 138         /* Bringup UART0 out of reset */
 139         REG(UART0_PWREMU_MGMT) = 0x0000e003;
 140
 141         /* Enable GIO3.3V cells used for EMAC */
 142         REG(VDD3P3V_PWDN) = 0;
 143
 144         /* Enable UART0 MUX lines */
 145         REG(PINMUX1) |= 1;
 146
 147         /* Enable EMAC and AEMIF pins */
 148         REG(PINMUX0) = 0x80000c1f;
 149
 150         /* Enable I2C pin Mux */
 151         REG(PINMUX1) |= (1 << 7);
 152
 153         /* Set the Bus Priority Register to appropriate value */
 154         REG(VBPR) = 0x20;
 155
 156         timer_init();
 157
 158         return(0);
 159 }
 160
 161 int misc_init_r (void)
 162 {
 163         u_int8_t        tmp[20], buf[10];
 164         int             i = 0;
 165         int             clk = 0;
 166
 167         /* Set serial number from UID chip */
 168         u_int8_t        crc_tbl[256] = {
 169                         0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
 170                         0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
 171                         0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
 172                         0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
 173                         0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
 174                         0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
 175                         0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
 176                         0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
 177                         0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
 178                         0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
 179                         0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
 180                         0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
 181                         0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
 182                         0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
 183                         0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
 184                         0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
 185                         0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
 186                         0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
 187                         0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
 188                         0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
 189                         0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
 190                         0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
 191                         0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
 192                         0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
 193                         0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
 194                         0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
 195                         0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
 196                         0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
 197                         0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
 198                         0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
 199                         0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
 200                         0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
 201                 };
 202
 203         clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
 204
 205         printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
 206         printf ("DDR Clock : %dMHz\n", (clk / 2));
 207
 208         /* Set serial number from UID chip */
 209         if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) {
 210                 printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
 211                 forceenv("serial#", "FAILED");
 212         } else {
 213                 if (buf[0] != 0x70) {   /* Device Family Code */
 214                         printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
 215                         forceenv("serial#", "FAILED");
 216                 }
 217         }
 218         /* Now check CRC */
 219         tmp[0] = 0;
 220         for (i = 0; i < 8; i++)
 221                 tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
 222
 223         if (tmp[0] != 0) {
 224                 printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR);
 225                 forceenv("serial#", "FAILED");
 226         } else {
 227                 /* CRC OK, set "serial" env variable */
 228                 sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
 229                         buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
 230                 forceenv("serial#", (char *)&tmp[0]);
 231         }
 232
 233         if (!eth_hw_init()) {
 234                 printf("ethernet init failed!\n");
 235         } else {
 236                 printf("ETH PHY   : %s\n", phy.name);
 237         }
 238
 239         return(0);
 240 }
 241
 242 int dram_init(void)
 243 {
 244         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 245         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 246
 247         return(0);
 248 }