2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
30 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
35 /* fpga configuration data - generated by bin2cc */
36 const unsigned char fpgadata[] =
38 #ifdef CONFIG_CPCI405_VER2
39 # ifdef CONFIG_CPCI405AB
40 # include "fpgadata_cpci405ab.c"
42 # include "fpgadata_cpci4052.c"
45 # include "fpgadata_cpci405.c"
50 * include common fpga code (for esd boards)
52 #include "../common/fpga.c"
56 int cpci405_version(void);
57 int gunzip(void *, int, unsigned char *, int *);
60 int board_pre_init (void)
62 #ifndef CONFIG_CPCI405_VER2
68 DECLARE_GLOBAL_DATA_PTR;
70 /* set up serial port with default baudrate */
72 gd->baudrate = CONFIG_BAUDRATE;
78 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
80 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
81 out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
82 out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
83 out32(GPIO0_OR, 0); /* pull prg low */
88 #ifndef CONFIG_CPCI405_VER2
89 if (cpci405_version() == 1) {
90 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
92 /* booting FPGA failed */
94 DECLARE_GLOBAL_DATA_PTR;
96 /* set up serial port with default baudrate */
98 gd->baudrate = CONFIG_BAUDRATE;
102 printf("\nFPGA: Booting failed ");
104 case ERROR_FPGA_PRG_INIT_LOW:
105 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
107 case ERROR_FPGA_PRG_INIT_HIGH:
108 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
110 case ERROR_FPGA_PRG_DONE:
111 printf("(Timeout: DONE not high after programming FPGA)\n ");
115 /* display infos on fpgaimage */
117 for (i=0; i<4; i++) {
118 len = fpgadata[index];
119 printf("FPGA: %s\n", &(fpgadata[index+1]));
124 for (i=20; i>0; i--) {
125 printf("Rebooting in %2d seconds \r",i);
126 for (index=0;index<1000;index++)
130 do_reset(NULL, 0, 0, NULL);
133 #endif /* !CONFIG_CPCI405_VER2 */
136 * IRQ 0-15 405GP internally generated; active high; level sensitive
137 * IRQ 16 405GP internally generated; active low; level sensitive
139 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
140 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
141 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
142 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
143 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
144 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
145 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
147 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
148 mtdcr(uicer, 0x00000000); /* disable all ints */
149 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
150 if (cpci405_version() == 3) {
151 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
153 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
155 mtdcr(uictr, 0x10000000); /* set int trigger levels */
156 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
157 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
163 /* ------------------------------------------------------------------------- */
167 #ifdef CONFIG_CPCI405_VER2
168 return 0; /* no, board is cpci405 */
170 if ((*(unsigned char *)0xf0000400 == 0x00) &&
171 (*(unsigned char *)0xf0000401 == 0x01))
172 return 0; /* no, board is cpci405 */
174 return -1; /* yes, board is cterm-m2 */
179 int cpci405_host(void)
181 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
182 return -1; /* yes, board is cpci405 host */
184 return 0; /* no, board is cpci405 adapter */
188 int cpci405_version(void)
190 unsigned long cntrl0Reg;
194 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
196 cntrl0Reg = mfdcr(cntrl0);
197 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
198 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
199 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
200 udelay(1000); /* wait some time before reading input */
201 value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
204 * Restore GPIO settings
206 mtdcr(cntrl0, cntrl0Reg);
210 /* CS2==1 && CS3==1 -> version 1 */
213 /* CS2==0 && CS3==1 -> version 2 */
216 /* CS2==1 && CS3==0 -> version 3 */
219 /* CS2==0 && CS3==0 -> version 4 */
222 /* should not be reached! */
228 int misc_init_f (void)
230 return 0; /* dummy implementation */
234 int misc_init_r (void)
236 DECLARE_GLOBAL_DATA_PTR;
239 char * tmp; /* Temporary char pointer */
240 unsigned long cntrl0Reg;
242 #ifdef CONFIG_CPCI405_VER2
244 ulong len = sizeof(fpgadata);
250 * On CPCI-405 version 2 the environment is saved in eeprom!
251 * FPGA can be gzip compressed (malloc) and booted this late.
254 if (cpci405_version() >= 2) {
256 * Setup GPIO pins (CS6+CS7 as GPIO)
258 cntrl0Reg = mfdcr(cntrl0);
259 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
261 dst = malloc(CFG_FPGA_MAX_SIZE);
262 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
263 printf ("GUNZIP ERROR - must RESET board to recover\n");
264 do_reset (NULL, 0, 0, NULL);
267 status = fpga_boot(dst, len);
269 printf("\nFPGA: Booting failed ");
271 case ERROR_FPGA_PRG_INIT_LOW:
272 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
274 case ERROR_FPGA_PRG_INIT_HIGH:
275 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
277 case ERROR_FPGA_PRG_DONE:
278 printf("(Timeout: DONE not high after programming FPGA)\n ");
282 /* display infos on fpgaimage */
284 for (i=0; i<4; i++) {
286 printf("FPGA: %s\n", &(dst[index+1]));
291 for (i=20; i>0; i--) {
292 printf("Rebooting in %2d seconds \r",i);
293 for (index=0;index<1000;index++)
297 do_reset(NULL, 0, 0, NULL);
300 /* restore gpio/cs settings */
301 mtdcr(cntrl0, cntrl0Reg);
305 /* display infos on fpgaimage */
307 for (i=0; i<4; i++) {
309 printf("%s ", &(dst[index+1]));
317 * Reset FPGA via FPGA_DATA pin
319 SET_FPGA(FPGA_PRG | FPGA_CLK);
320 udelay(1000); /* wait 1ms */
321 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
322 udelay(1000); /* wait 1ms */
324 if (cpci405_version() == 3) {
325 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
326 volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
329 * Enable outputs in fpga on version 3 board
331 *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
339 * Reset external DUART
341 *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
343 *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
347 puts("\n*** U-Boot Version does not match Board Version!\n");
348 puts("*** CPCI-405 Version 1.x detected!\n");
349 puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
352 #else /* CONFIG_CPCI405_VER2 */
355 * Generate last byte of ip-addr from code-plug @ 0xf0000400
359 unsigned char ipbyte = *(unsigned char *)0xf0000400;
362 * Only overwrite ip-addr with allowed values
364 if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
365 bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
366 sprintf(str, "%ld.%ld.%ld.%ld",
367 (bd->bi_ip_addr & 0xff000000) >> 24,
368 (bd->bi_ip_addr & 0x00ff0000) >> 16,
369 (bd->bi_ip_addr & 0x0000ff00) >> 8,
370 (bd->bi_ip_addr & 0x000000ff));
371 setenv("ipaddr", str);
375 if (cpci405_version() >= 2) {
376 puts("\n*** U-Boot Version does not match Board Version!\n");
377 puts("*** CPCI-405 Board Version 2.x detected!\n");
378 puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
381 #endif /* CONFIG_CPCI405_VER2 */
384 * Select cts (and not dsr) on uart1
386 cntrl0Reg = mfdcr(cntrl0);
387 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
390 * Write ethernet addr in NVRAM for VxWorks
392 tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
393 memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
399 * Check Board Identity:
402 int checkboard (void)
404 #ifndef CONFIG_CPCI405_VER2
408 unsigned char str[64];
409 int i = getenv_r ("serial#", str, sizeof(str));
415 puts ("### No HW ID - assuming CPCI405");
420 ver = cpci405_version();
421 printf(" (Ver %d.x, ", ver);
423 #if 0 /* test-only */
425 volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
427 if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
428 puts ("FLASH Bank B, ");
430 puts ("FLASH Bank A, ");
436 unsigned char str[4];
439 * Read board-id and save in env-variable
441 sprintf(str, "%d", *(unsigned char *)0xf0000400);
442 setenv("boardid", str);
443 printf("CTERM-M2 - Id=%s)", str);
445 if (cpci405_host()) {
446 puts ("PCI Host Version)");
448 puts ("PCI Adapter Version)");
452 #ifndef CONFIG_CPCI405_VER2
455 /* display infos on fpgaimage */
457 for (i=0; i<4; i++) {
458 len = fpgadata[index];
459 printf("%s ", &(fpgadata[index+1]));
469 /* ------------------------------------------------------------------------- */
471 long int initdram (int board_type)
475 mtdcr(memcfga, mem_mb0cf);
476 val = mfdcr(memcfgd);
479 printf("\nmb0cf=%x\n", val); /* test-only */
480 printf("strap=%x\n", mfdcr(strap)); /* test-only */
483 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
486 /* ------------------------------------------------------------------------- */
490 /* TODO: XXX XXX XXX */
491 printf ("test: 16 MB - ok\n");
496 /* ------------------------------------------------------------------------- */
498 #ifdef CONFIG_CPCI405_VER2
499 #ifdef CONFIG_IDE_RESET
501 void ide_set_reset(int on)
503 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
506 * Assert or deassert CompactFlash Reset Pin
508 if (on) { /* assert RESET */
509 *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
510 } else { /* release RESET */
511 *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
515 #endif /* CONFIG_IDE_RESET */
516 #endif /* CONFIG_CPCI405_VER2 */
519 #ifdef CONFIG_CPCI405AB
521 #define ONE_WIRE_CLEAR (*(volatile unsigned short *)0xf0400000 |= 0x0100)
522 #define ONE_WIRE_SET (*(volatile unsigned short *)0xf0400000 &= ~0x0100)
523 #define ONE_WIRE_GET (*(volatile unsigned short *)0xf0400002 & 0x1000)
526 * Generate a 1-wire reset, return 1 if no presence detect was found,
527 * return 0 otherwise.
528 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
530 int OWTouchReset(void)
539 result = ONE_WIRE_GET;
547 * Send 1 a 1-wire write bit.
548 * Provide 10us recovery time.
550 void OWWriteBit(int bit)
573 * Read a bit from the 1-wire bus and return it.
574 * Provide 10us recovery time.
585 result = ONE_WIRE_GET;
592 void OWWriteByte(int data)
596 for (loop=0; loop<8; loop++) {
597 OWWriteBit(data & 0x01);
605 int loop, result = 0;
607 for (loop=0; loop<8; loop++) {
618 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
620 volatile unsigned short val;
623 unsigned char ow_id[6];
624 unsigned char str[32];
625 unsigned char ow_crc;
628 * Clear 1-wire bit (open drain with pull-up)
630 val = *(volatile unsigned short *)0xf0400000;
631 val &= ~0x1000; /* clear 1-wire bit */
632 *(volatile unsigned short *)0xf0400000 = val;
634 result = OWTouchReset();
636 puts("No 1-wire device detected!\n");
639 OWWriteByte(0x33); /* send read rom command */
640 OWReadByte(); /* skip family code ( == 0x01) */
641 for (i=0; i<6; i++) {
642 ow_id[i] = OWReadByte();
644 ow_crc = OWReadByte(); /* read crc */
646 sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
647 printf("Setting environment variable 'ow_id' to %s\n", str);
648 setenv("ow_id", str);
653 onewire, 1, 1, do_onewire,
654 "onewire - Read 1-write ID\n",
658 #endif /* CONFIG_CPCI405AB */