2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
37 /* fpga configuration data - generated by bin2cc */
38 const unsigned char fpgadata[] =
40 #ifdef CONFIG_CPCI405_VER2
41 # ifdef CONFIG_CPCI405AB
42 # include "fpgadata_cpci405ab.c"
44 # include "fpgadata_cpci4052.c"
47 # include "fpgadata_cpci405.c"
52 * include common fpga code (for esd boards)
54 #include "../common/fpga.c"
57 #include "../common/auto_update.h"
59 #ifdef CONFIG_CPCI405AB
60 au_image_t au_image[] = {
61 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
62 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
63 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
64 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
65 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
68 #ifdef CONFIG_CPCI405_VER2
69 au_image_t au_image[] = {
70 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
71 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
72 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
73 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
74 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
77 au_image_t au_image[] = {
78 {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
79 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
80 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
81 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
82 {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
87 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
91 int cpci405_version(void);
92 int gunzip(void *, int, unsigned char *, unsigned long *);
93 void lxt971_no_sleep(void);
96 int board_early_init_f (void)
98 #ifndef CONFIG_CPCI405_VER2
104 /* set up serial port with default baudrate */
105 (void) get_clocks ();
106 gd->baudrate = CONFIG_BAUDRATE;
112 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
114 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
115 out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
116 out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
117 out32(GPIO0_OR, 0); /* pull prg low */
122 #ifndef CONFIG_CPCI405_VER2
123 if (cpci405_version() == 1) {
124 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
126 /* booting FPGA failed */
128 /* set up serial port with default baudrate */
129 (void) get_clocks ();
130 gd->baudrate = CONFIG_BAUDRATE;
134 printf("\nFPGA: Booting failed ");
136 case ERROR_FPGA_PRG_INIT_LOW:
137 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
139 case ERROR_FPGA_PRG_INIT_HIGH:
140 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
142 case ERROR_FPGA_PRG_DONE:
143 printf("(Timeout: DONE not high after programming FPGA)\n ");
147 /* display infos on fpgaimage */
149 for (i=0; i<4; i++) {
150 len = fpgadata[index];
151 printf("FPGA: %s\n", &(fpgadata[index+1]));
156 for (i=20; i>0; i--) {
157 printf("Rebooting in %2d seconds \r",i);
158 for (index=0;index<1000;index++)
162 do_reset(NULL, 0, 0, NULL);
165 #endif /* !CONFIG_CPCI405_VER2 */
168 * IRQ 0-15 405GP internally generated; active high; level sensitive
169 * IRQ 16 405GP internally generated; active low; level sensitive
171 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
172 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
173 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
174 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
175 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
176 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
177 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
179 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
180 mtdcr(uicer, 0x00000000); /* disable all ints */
181 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
182 if (cpci405_version() == 3) {
183 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
185 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
187 mtdcr(uictr, 0x10000000); /* set int trigger levels */
188 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
189 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
195 /* ------------------------------------------------------------------------- */
199 #ifdef CONFIG_CPCI405_VER2
200 return 0; /* no, board is cpci405 */
202 if ((*(unsigned char *)0xf0000400 == 0x00) &&
203 (*(unsigned char *)0xf0000401 == 0x01))
204 return 0; /* no, board is cpci405 */
206 return -1; /* yes, board is cterm-m2 */
211 int cpci405_host(void)
213 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
214 return -1; /* yes, board is cpci405 host */
216 return 0; /* no, board is cpci405 adapter */
220 int cpci405_version(void)
222 unsigned long cntrl0Reg;
226 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
228 cntrl0Reg = mfdcr(cntrl0);
229 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
230 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
231 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
232 udelay(1000); /* wait some time before reading input */
233 value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
236 * Restore GPIO settings
238 mtdcr(cntrl0, cntrl0Reg);
242 /* CS2==1 && CS3==1 -> version 1 */
245 /* CS2==0 && CS3==1 -> version 2 */
248 /* CS2==1 && CS3==0 -> version 3 */
251 /* CS2==0 && CS3==0 -> version 4 */
254 /* should not be reached! */
260 int misc_init_f (void)
262 return 0; /* dummy implementation */
266 int misc_init_r (void)
268 unsigned long cntrl0Reg;
270 /* adjust flash start and offset */
271 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
272 gd->bd->bi_flashoffset = 0;
274 #ifdef CONFIG_CPCI405_VER2
277 ulong len = sizeof(fpgadata);
283 * On CPCI-405 version 2 the environment is saved in eeprom!
284 * FPGA can be gzip compressed (malloc) and booted this late.
287 if (cpci405_version() >= 2) {
289 * Setup GPIO pins (CS6+CS7 as GPIO)
291 cntrl0Reg = mfdcr(cntrl0);
292 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
294 dst = malloc(CFG_FPGA_MAX_SIZE);
295 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
296 printf ("GUNZIP ERROR - must RESET board to recover\n");
297 do_reset (NULL, 0, 0, NULL);
300 status = fpga_boot(dst, len);
302 printf("\nFPGA: Booting failed ");
304 case ERROR_FPGA_PRG_INIT_LOW:
305 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
307 case ERROR_FPGA_PRG_INIT_HIGH:
308 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
310 case ERROR_FPGA_PRG_DONE:
311 printf("(Timeout: DONE not high after programming FPGA)\n ");
315 /* display infos on fpgaimage */
317 for (i=0; i<4; i++) {
319 printf("FPGA: %s\n", &(dst[index+1]));
324 for (i=20; i>0; i--) {
325 printf("Rebooting in %2d seconds \r",i);
326 for (index=0;index<1000;index++)
330 do_reset(NULL, 0, 0, NULL);
333 /* restore gpio/cs settings */
334 mtdcr(cntrl0, cntrl0Reg);
338 /* display infos on fpgaimage */
340 for (i=0; i<4; i++) {
342 printf("%s ", &(dst[index+1]));
350 * Reset FPGA via FPGA_DATA pin
352 SET_FPGA(FPGA_PRG | FPGA_CLK);
353 udelay(1000); /* wait 1ms */
354 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
355 udelay(1000); /* wait 1ms */
357 if (cpci405_version() == 3) {
358 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
359 volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
362 * Enable outputs in fpga on version 3 board
364 *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
372 * Reset external DUART
374 *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
376 *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
380 puts("\n*** U-Boot Version does not match Board Version!\n");
381 puts("*** CPCI-405 Version 1.x detected!\n");
382 puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
386 #else /* CONFIG_CPCI405_VER2 */
388 #if 0 /* test-only: code-plug now not relavant for ip-address any more */
390 * Generate last byte of ip-addr from code-plug @ 0xf0000400
394 unsigned char ipbyte = *(unsigned char *)0xf0000400;
397 * Only overwrite ip-addr with allowed values
399 if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
400 bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
401 sprintf(str, "%ld.%ld.%ld.%ld",
402 (bd->bi_ip_addr & 0xff000000) >> 24,
403 (bd->bi_ip_addr & 0x00ff0000) >> 16,
404 (bd->bi_ip_addr & 0x0000ff00) >> 8,
405 (bd->bi_ip_addr & 0x000000ff));
406 setenv("ipaddr", str);
411 if (cpci405_version() >= 2) {
412 puts("\n*** U-Boot Version does not match Board Version!\n");
413 puts("*** CPCI-405 Board Version 2.x detected!\n");
414 puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
417 #endif /* CONFIG_CPCI405_VER2 */
420 * Select cts (and not dsr) on uart1
422 cntrl0Reg = mfdcr(cntrl0);
423 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
430 * Check Board Identity:
433 int checkboard (void)
435 #ifndef CONFIG_CPCI405_VER2
440 int i = getenv_r ("serial#", str, sizeof(str));
446 puts ("### No HW ID - assuming CPCI405");
451 ver = cpci405_version();
452 printf(" (Ver %d.x, ", ver);
454 #if 0 /* test-only */
456 volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
458 if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
459 puts ("FLASH Bank B, ");
461 puts ("FLASH Bank A, ");
470 * Read board-id and save in env-variable
472 sprintf(str, "%d", *(unsigned char *)0xf0000400);
473 setenv("boardid", str);
474 printf("CTERM-M2 - Id=%s)", str);
476 if (cpci405_host()) {
477 puts ("PCI Host Version)");
479 puts ("PCI Adapter Version)");
483 #ifndef CONFIG_CPCI405_VER2
486 /* display infos on fpgaimage */
488 for (i=0; i<4; i++) {
489 len = fpgadata[index];
490 printf("%s ", &(fpgadata[index+1]));
498 * Disable sleep mode in LXT971
505 /* ------------------------------------------------------------------------- */
507 long int initdram (int board_type)
511 mtdcr(memcfga, mem_mb0cf);
512 val = mfdcr(memcfgd);
515 printf("\nmb0cf=%x\n", val); /* test-only */
516 printf("strap=%x\n", mfdcr(strap)); /* test-only */
519 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
522 /* ------------------------------------------------------------------------- */
526 /* TODO: XXX XXX XXX */
527 printf ("test: 16 MB - ok\n");
532 /* ------------------------------------------------------------------------- */
534 #ifdef CONFIG_CPCI405_VER2
535 #ifdef CONFIG_IDE_RESET
537 void ide_set_reset(int on)
539 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
542 * Assert or deassert CompactFlash Reset Pin
544 if (on) { /* assert RESET */
545 *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
546 } else { /* release RESET */
547 *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
551 #endif /* CONFIG_IDE_RESET */
552 #endif /* CONFIG_CPCI405_VER2 */
555 #ifdef CONFIG_CPCI405AB
557 #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
558 |= CFG_FPGA_MODE_1WIRE_DIR)
559 #define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
560 &= ~CFG_FPGA_MODE_1WIRE_DIR)
561 #define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
562 & CFG_FPGA_MODE_1WIRE)
565 * Generate a 1-wire reset, return 1 if no presence detect was found,
566 * return 0 otherwise.
567 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
569 int OWTouchReset(void)
578 result = ONE_WIRE_GET;
586 * Send 1 a 1-wire write bit.
587 * Provide 10us recovery time.
589 void OWWriteBit(int bit)
612 * Read a bit from the 1-wire bus and return it.
613 * Provide 10us recovery time.
624 result = ONE_WIRE_GET;
631 void OWWriteByte(int data)
635 for (loop=0; loop<8; loop++) {
636 OWWriteBit(data & 0x01);
644 int loop, result = 0;
646 for (loop=0; loop<8; loop++) {
657 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
659 volatile unsigned short val;
662 unsigned char ow_id[6];
664 unsigned char ow_crc;
667 * Clear 1-wire bit (open drain with pull-up)
669 val = *(volatile unsigned short *)0xf0400000;
670 val &= ~0x1000; /* clear 1-wire bit */
671 *(volatile unsigned short *)0xf0400000 = val;
673 result = OWTouchReset();
675 puts("No 1-wire device detected!\n");
678 OWWriteByte(0x33); /* send read rom command */
679 OWReadByte(); /* skip family code ( == 0x01) */
680 for (i=0; i<6; i++) {
681 ow_id[i] = OWReadByte();
683 ow_crc = OWReadByte(); /* read crc */
685 sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
686 printf("Setting environment variable 'ow_id' to %s\n", str);
687 setenv("ow_id", str);
692 onewire, 1, 1, do_onewire,
693 "onewire - Read 1-write ID\n",
698 #define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
699 #define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
702 * Write backplane ip-address...
704 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
713 buf = malloc(CFG_ENV_SIZE_2);
714 if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
715 puts("\nError reading backplane EEPROM!\n");
717 crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
718 if (crc != *(ulong *)buf) {
719 printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
726 ptr = strstr(buf+4, "bp_ip=");
728 printf("ERROR: bp_ip not found!\n");
732 ipaddr = string_to_ip(ptr);
735 * Update whole ip-addr
737 bd->bi_ip_addr = ipaddr;
738 sprintf(str, "%ld.%ld.%ld.%ld",
739 (bd->bi_ip_addr & 0xff000000) >> 24,
740 (bd->bi_ip_addr & 0x00ff0000) >> 16,
741 (bd->bi_ip_addr & 0x0000ff00) >> 8,
742 (bd->bi_ip_addr & 0x000000ff));
743 setenv("ipaddr", str);
744 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
752 getbpip, 1, 1, do_get_bpip,
753 "getbpip - Update IP-Address with Backplane IP-Address\n",
758 * Set and print backplane ip...
760 int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
771 printf("Setting bp_ip to %s\n", argv[1]);
772 buf = malloc(CFG_ENV_SIZE_2);
773 memset(buf, 0, CFG_ENV_SIZE_2);
774 sprintf(str, "bp_ip=%s", argv[1]);
776 crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
779 if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
780 puts("\nError writing backplane EEPROM!\n");
788 setbpip, 2, 1, do_set_bpip,
789 "setbpip - Write Backplane IP-Address\n",
793 #endif /* CONFIG_CPCI405AB */