2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/errno.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_portals.h>
20 #include <asm/fsl_liodn.h>
23 #include "../common/qixis.h"
24 #include "../common/vsc3316_3308.h"
25 #include "../common/idt8t49n222a_serdes_clk.h"
26 #include "../common/zm7300.h"
28 #include "b4860qds_qixis.h"
29 #include "b4860qds_crossbar_con.h"
31 #define CLK_MUX_SEL_MASK 0x4
32 #define ETH_PHY_CLK_OUT 0x4
34 DECLARE_GLOBAL_DATA_PTR;
40 struct cpu_type *cpu = gd->arch.cpu;
41 static const char *const freq[] = {"100", "125", "156.25", "161.13",
42 "122.88", "122.88", "122.88"};
45 printf("Board: %sQDS, ", cpu->name);
46 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
47 QIXIS_READ(id), QIXIS_READ(arch));
49 sw = QIXIS_READ(brdcfg[0]);
50 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
53 printf("vBank: %d\n", sw);
54 else if (sw >= 0x8 && sw <= 0xE)
57 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
59 printf("FPGA: v%d (%s), build %d",
60 (int)QIXIS_READ(scver), qixis_read_tag(buf),
61 (int)qixis_read_minor());
62 /* the timestamp string contains "\n" at the end */
63 printf(" on %s", qixis_read_time(buf));
66 * Display the actual SERDES reference clocks as configured by the
67 * dip switches on the board. Note that the SWx registers could
68 * technically be set to force the reference clocks to match the
69 * values that the SERDES expects (or vice versa). For now, however,
70 * we just display both values and hope the user notices when they
73 puts("SERDES Reference Clocks: ");
74 sw = QIXIS_READ(brdcfg[2]);
75 clock = (sw >> 5) & 7;
76 printf("Bank1=%sMHz ", freq[clock]);
77 sw = QIXIS_READ(brdcfg[4]);
78 clock = (sw >> 6) & 3;
79 printf("Bank2=%sMHz\n", freq[clock]);
84 int select_i2c_ch_pca(u8 ch)
88 /* Selecting proper channel via PCA*/
89 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
91 printf("PCA: failed to select proper channel.\n");
99 * read_voltage from sensor on I2C bus
100 * We use average of 4 readings, waiting for 532us befor another reading
102 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
103 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
105 static inline int read_voltage(void)
107 int i, ret, voltage_read = 0;
110 for (i = 0; i < NUM_READINGS; i++) {
111 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
112 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
114 printf("VID: failed to read core voltage\n");
117 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
118 printf("VID: Core voltage sensor error\n");
121 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
123 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
124 udelay(WAIT_FOR_ADC);
126 /* calculate the average */
127 voltage_read /= NUM_READINGS;
132 static int adjust_vdd(ulong vdd_override)
134 int re_enable = disable_interrupts();
135 ccsr_gur_t __iomem *gur =
136 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
139 int vdd_target, vdd_last;
140 int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
142 unsigned int orig_i2c_speed;
143 unsigned long vdd_string_override;
145 static const uint16_t vdd[32] = {
178 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
180 printf("VID: I2c failed to switch channel\n");
185 /* get the voltage ID from fuse status register */
186 fusesr = in_be32(&gur->dcfg_fusesr);
187 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
188 FSL_CORENET_DCFG_FUSESR_VID_MASK;
189 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
190 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
191 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
193 vdd_target = vdd[vid];
194 debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
197 /* check override variable for overriding VDD */
198 vdd_string = getenv("b4qds_vdd_mv");
199 if (vdd_override == 0 && vdd_string &&
200 !strict_strtoul(vdd_string, 10, &vdd_string_override))
201 vdd_override = vdd_string_override;
202 if (vdd_override >= 819 && vdd_override <= 1212) {
203 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
204 debug("VDD override is %lu\n", vdd_override);
205 } else if (vdd_override != 0) {
206 printf("Invalid value.\n");
209 if (vdd_target == 0) {
210 printf("VID: VID not used\n");
216 * Read voltage monitor to check real voltage.
217 * Voltage monitor LSB is 4mv.
219 vdd_last = read_voltage();
221 printf("VID: abort VID adjustment\n");
226 debug("VID: Core voltage is at %d mV\n", vdd_last);
227 ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
229 printf("VID: I2c failed to switch channel to DPM\n");
234 /* Round up to the value of step of Voltage regulator */
235 voltage = roundup(vdd_target, ZM_STEP);
236 debug("VID: rounded up voltage = %d\n", voltage);
238 /* lower the speed to 100kHz to access ZM7300 device */
239 debug("VID: Setting bus speed to 100KHz if not already set\n");
240 orig_i2c_speed = i2c_get_bus_speed();
241 if (orig_i2c_speed != 100000)
242 i2c_set_bus_speed(100000);
244 /* Read the existing level on board, if equal to requsted one,
246 existing_voltage = zm_read_voltage();
248 /* allowing the voltage difference of one step 0.0125V acceptable */
249 if ((existing_voltage >= voltage) &&
250 (existing_voltage < (voltage + ZM_STEP))) {
251 debug("VID: voltage already set as requested,returning\n");
252 ret = existing_voltage;
255 debug("VID: Changing voltage for board from %dmV to %dmV\n",
256 existing_voltage/10, voltage/10);
258 if (zm_disable_wp() < 0) {
262 /* Change Voltage: the change is done through all the steps in the
263 way, to avoid reset to the board due to power good signal fail
264 in big voltage change gap jump.
266 if (existing_voltage > voltage) {
267 temp_voltage = existing_voltage - ZM_STEP;
268 while (temp_voltage >= voltage) {
269 ret = zm_write_voltage(temp_voltage);
270 if (ret == temp_voltage) {
271 temp_voltage -= ZM_STEP;
273 /* ZM7300 device failed to set
276 ("VID:Stepping down vol failed:%dmV\n",
283 temp_voltage = existing_voltage + ZM_STEP;
284 while (temp_voltage < (voltage + ZM_STEP)) {
285 ret = zm_write_voltage(temp_voltage);
286 if (ret == temp_voltage) {
287 temp_voltage += ZM_STEP;
289 /* ZM7300 device failed to set
292 ("VID:Stepping up vol failed:%dmV\n",
300 if (zm_enable_wp() < 0)
303 /* restore the speed to 400kHz */
304 out: debug("VID: Restore the I2C bus speed to %dKHz\n",
305 orig_i2c_speed/1000);
306 i2c_set_bus_speed(orig_i2c_speed);
310 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
312 printf("VID: I2c failed to switch channel\n");
316 vdd_last = read_voltage();
317 select_i2c_ch_pca(I2C_CH_DEFAULT);
320 printf("VID: Core voltage %d mV\n", vdd_last);
330 int configure_vsc3316_3308(void)
332 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
333 unsigned int num_vsc16_con, num_vsc08_con;
334 u32 serdes1_prtcl, serdes2_prtcl;
337 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
338 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
339 if (!serdes1_prtcl) {
340 printf("SERDES1 is not enabled\n");
343 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
344 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
346 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
347 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
348 if (!serdes2_prtcl) {
349 printf("SERDES2 is not enabled\n");
352 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
353 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
355 switch (serdes1_prtcl) {
365 * Lanes: C,D,E,F,G,H: CPRI
367 debug("Configuring crossbar to use onboard SGMII PHYs:"
368 "srds_prctl:%x\n", serdes1_prtcl);
369 num_vsc16_con = NUM_CON_VSC3316;
370 /* Configure VSC3316 crossbar switch */
371 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
373 ret = vsc3316_config(VSC3316_TX_ADDRESS,
374 vsc16_tx_4sfp_sgmii_12_56,
378 ret = vsc3316_config(VSC3316_RX_ADDRESS,
379 vsc16_rx_4sfp_sgmii_12_56,
415 * Lanes: E,F,G,H: CPRI
417 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
418 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
419 num_vsc16_con = NUM_CON_VSC3316;
420 /* Configure VSC3316 crossbar switch */
421 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
423 ret = vsc3316_config(VSC3316_TX_ADDRESS,
424 vsc16_tx_sfp_sgmii_aurora,
428 ret = vsc3316_config(VSC3316_RX_ADDRESS,
429 vsc16_rx_sfp_sgmii_aurora,
438 #ifdef CONFIG_PPC_B4420
444 * Lanes: A,B,C,D: SGMII
445 * Lanes: E,F,G,H: CPRI
447 debug("Configuring crossbar to use onboard SGMII PHYs:"
448 "srds_prctl:%x\n", serdes1_prtcl);
449 num_vsc16_con = NUM_CON_VSC3316;
450 /* Configure VSC3316 crossbar switch */
451 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
453 ret = vsc3316_config(VSC3316_TX_ADDRESS,
454 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
457 ret = vsc3316_config(VSC3316_RX_ADDRESS,
458 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
471 num_vsc16_con = NUM_CON_VSC3316;
472 /* Configure VSC3316 crossbar switch */
473 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
475 ret = vsc3316_config(VSC3316_TX_ADDRESS,
476 vsc16_tx_sfp, num_vsc16_con);
479 ret = vsc3316_config(VSC3316_RX_ADDRESS,
480 vsc16_rx_sfp, num_vsc16_con);
488 printf("WARNING:VSC crossbars programming not supported for:%x"
489 " SerDes1 Protocol.\n", serdes1_prtcl);
493 num_vsc08_con = NUM_CON_VSC3308;
494 /* Configure VSC3308 crossbar switch */
495 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
496 switch (serdes2_prtcl) {
497 #ifdef CONFIG_PPC_B4420
509 ret = vsc3308_config(VSC3308_TX_ADDRESS,
510 vsc08_tx_amc, num_vsc08_con);
513 ret = vsc3308_config(VSC3308_RX_ADDRESS,
514 vsc08_rx_amc, num_vsc08_con);
539 ret = vsc3308_config(VSC3308_TX_ADDRESS,
540 vsc08_tx_sfp, num_vsc08_con);
543 ret = vsc3308_config(VSC3308_RX_ADDRESS,
544 vsc08_rx_sfp, num_vsc08_con);
552 printf("WARNING:VSC crossbars programming not supported for: %x"
553 " SerDes2 Protocol.\n", serdes2_prtcl);
560 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
564 /* Steps For SerDes PLLs reset and reconfiguration
565 * or PLL power-up procedure
567 debug("CALIBRATE PLL:%d\n", pll_num);
568 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
569 SRDS_RSTCTL_SDRST_B);
571 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
572 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
574 setbits_be32(&srds_regs->bank[pll_num].rstctl,
576 setbits_be32(&srds_regs->bank[pll_num].rstctl,
577 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
578 | SRDS_RSTCTL_SDRST_B));
582 /* Check whether PLL has been locked or not */
583 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
585 rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
586 debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
593 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
596 u32 fcap, dcbias, bcap, pllcr1, pllcr0;
598 if (calibrate_pll(srds_regs, pll_num)) {
600 /* Read fcap, dcbias and bcap value */
601 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
602 SRDS_PLLCR0_DCBIAS_OUT_EN);
603 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
605 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
606 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
608 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
609 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
610 SRDS_PLLCR0_DCBIAS_OUT_EN);
611 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
613 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
614 debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
616 if (fcap == 0 && bcap == 1) {
618 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
619 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
620 | SRDS_RSTCTL_SDRST_B));
621 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
622 SRDS_PLLCR1_BCAP_EN);
623 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
624 SRDS_PLLCR1_BCAP_OVD);
625 if (calibrate_pll(srds_regs, pll_num)) {
626 /*save the fcap, dcbias and bcap values*/
627 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
628 SRDS_PLLCR0_DCBIAS_OUT_EN);
629 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
631 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
632 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
633 & SRDS_PLLSR2_BCAP_EN;
634 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
635 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
636 SRDS_PLLCR0_DCBIAS_OUT_EN);
638 (&srds_regs->bank[pll_num].pllsr2) &
640 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
643 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
644 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
645 | SRDS_RSTCTL_SDRST_B));
646 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
647 SRDS_PLLCR1_BYP_CAL);
648 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
649 SRDS_PLLCR1_BCAP_EN);
650 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
651 SRDS_PLLCR1_BCAP_OVD);
652 /* change the fcap and dcbias to the saved
653 * values from Step 3 */
654 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
655 SRDS_PLLCR1_PLL_FCAP);
657 (&srds_regs->bank[pll_num].pllcr1)|
658 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
659 out_be32(&srds_regs->bank[pll_num].pllcr1,
661 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
662 SRDS_PLLCR0_DCBIAS_OVRD);
664 (&srds_regs->bank[pll_num].pllcr0)|
665 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
666 out_be32(&srds_regs->bank[pll_num].pllcr0,
668 ret = calibrate_pll(srds_regs, pll_num);
674 } else { /* Step 5 */
675 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
676 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
677 | SRDS_RSTCTL_SDRST_B));
679 /* Change the fcap, dcbias, and bcap to the
680 * values from Step 1 */
681 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
682 SRDS_PLLCR1_BYP_CAL);
683 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
684 SRDS_PLLCR1_PLL_FCAP);
685 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
686 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
687 out_be32(&srds_regs->bank[pll_num].pllcr1,
689 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
690 SRDS_PLLCR0_DCBIAS_OVRD);
691 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
692 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
693 out_be32(&srds_regs->bank[pll_num].pllcr0,
695 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
696 SRDS_PLLCR1_BCAP_EN);
697 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
698 SRDS_PLLCR1_BCAP_OVD);
699 ret = calibrate_pll(srds_regs, pll_num);
708 static int check_serdes_pll_locks(void)
710 serdes_corenet_t *srds1_regs =
711 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
712 serdes_corenet_t *srds2_regs =
713 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
716 debug("\nSerDes1 Lock check\n");
717 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
718 ret1 = check_pll_locks(srds1_regs, i);
720 printf("SerDes1, PLL:%d didnt lock\n", i);
724 debug("\nSerDes2 Lock check\n");
725 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
726 ret2 = check_pll_locks(srds2_regs, i);
728 printf("SerDes2, PLL:%d didnt lock\n", i);
736 int config_serdes1_refclks(void)
738 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
739 serdes_corenet_t *srds_regs =
740 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
741 u32 serdes1_prtcl, lane;
742 unsigned int flag_sgmii_aurora_prtcl = 0;
746 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
747 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
748 if (!serdes1_prtcl) {
749 printf("SERDES1 is not enabled\n");
752 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
753 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
755 /* To prevent generation of reset request from SerDes
756 * while changing the refclks, By setting SRDS_RST_MSK bit,
757 * SerDes reset event cannot cause a reset request
759 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
761 /* Reconfigure IDT idt8t49n222a device for CPRI to work
762 * For this SerDes1's Refclk1 and refclk2 need to be set
765 switch (serdes1_prtcl) {
793 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
794 " for srds_prctl:%x\n", serdes1_prtcl);
795 ret = select_i2c_ch_pca(I2C_CH_IDT);
797 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
798 SERDES_REFCLK_122_88,
799 SERDES_REFCLK_122_88, 0);
801 printf("IDT8T49N222A configuration failed.\n");
804 debug("IDT8T49N222A configured.\n");
808 select_i2c_ch_pca(I2C_CH_DEFAULT);
810 /* Change SerDes1's Refclk1 to 125MHz for on board
811 * SGMIIs or Aurora to work
813 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
814 enum srds_prtcl lane_prtcl = serdes_get_prtcl
815 (0, serdes1_prtcl, lane);
816 switch (lane_prtcl) {
817 case SGMII_FM1_DTSEC1:
818 case SGMII_FM1_DTSEC2:
819 case SGMII_FM1_DTSEC3:
820 case SGMII_FM1_DTSEC4:
821 case SGMII_FM1_DTSEC5:
822 case SGMII_FM1_DTSEC6:
824 flag_sgmii_aurora_prtcl++;
831 if (flag_sgmii_aurora_prtcl)
832 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
834 /* Steps For SerDes PLLs reset and reconfiguration after
835 * changing SerDes's refclks
837 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
838 debug("For PLL%d reset and reconfiguration after"
839 " changing refclks\n", i+1);
840 clrbits_be32(&srds_regs->bank[i].rstctl,
841 SRDS_RSTCTL_SDRST_B);
843 clrbits_be32(&srds_regs->bank[i].rstctl,
844 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
846 setbits_be32(&srds_regs->bank[i].rstctl,
848 setbits_be32(&srds_regs->bank[i].rstctl,
849 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
850 | SRDS_RSTCTL_SDRST_B));
854 printf("WARNING:IDT8T49N222A configuration not"
855 " supported for:%x SerDes1 Protocol.\n",
860 /* Clearing SRDS_RST_MSK bit as now
861 * SerDes reset event can cause a reset request
863 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
867 int config_serdes2_refclks(void)
869 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
870 serdes_corenet_t *srds2_regs =
871 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
876 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
877 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
878 if (!serdes2_prtcl) {
879 debug("SERDES2 is not enabled\n");
882 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
883 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
885 /* To prevent generation of reset request from SerDes
886 * while changing the refclks, By setting SRDS_RST_MSK bit,
887 * SerDes reset event cannot cause a reset request
889 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
891 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
892 * For this SerDes2's Refclk1 need to be set to 100MHz
894 switch (serdes2_prtcl) {
895 #ifdef CONFIG_PPC_B4420
903 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
905 ret = select_i2c_ch_pca(I2C_CH_IDT);
907 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
909 SERDES_REFCLK_156_25, 0);
911 printf("IDT8T49N222A configuration failed.\n");
914 debug("IDT8T49N222A configured.\n");
918 select_i2c_ch_pca(I2C_CH_DEFAULT);
920 /* Steps For SerDes PLLs reset and reconfiguration after
921 * changing SerDes's refclks
923 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
924 clrbits_be32(&srds2_regs->bank[i].rstctl,
925 SRDS_RSTCTL_SDRST_B);
927 clrbits_be32(&srds2_regs->bank[i].rstctl,
928 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
930 setbits_be32(&srds2_regs->bank[i].rstctl,
932 setbits_be32(&srds2_regs->bank[i].rstctl,
933 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
934 | SRDS_RSTCTL_SDRST_B));
940 printf("IDT configuration not supported for:%x S2 Protocol.\n",
945 /* Clearing SRDS_RST_MSK bit as now
946 * SerDes reset event can cause a reset request
948 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
952 int board_early_init_r(void)
954 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
955 int flash_esel = find_tlb_idx((void *)flashbase, 1);
957 u32 svr = SVR_SOC_VER(get_svr());
959 /* Create law for MAPLE only for personalities having MAPLE */
960 if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
961 (svr == SVR_B4420) || (svr == SVR_B4220)) {
962 set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
967 * Remap Boot flash + PROMJET region to caching-inhibited
968 * so that flash can be erased properly.
971 /* Flush d-cache and invalidate i-cache of any FLASH data */
975 if (flash_esel == -1) {
976 /* very unlikely unless something is messed up */
977 puts("Error: Could not find TLB for FLASH BASE\n");
978 flash_esel = 2; /* give our best effort to continue */
980 /* invalidate existing TLB entry for flash + promjet */
981 disable_tlb(flash_esel);
984 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
985 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
986 0, flash_esel, BOOKE_PAGESZ_256M, 1);
989 #ifdef CONFIG_SYS_DPAA_QBMAN
993 * Adjust core voltage according to voltage ID
994 * This function changes I2C mux to channel 2.
996 if (adjust_vdd(0) < 0)
997 printf("Warning: Adjusting core voltage failed\n");
999 /* SerDes1 refclks need to be set again, as default clks
1000 * are not suitable for CPRI and onboard SGMIIs to work
1002 * This function will set SerDes1's Refclk1 and refclk2
1003 * as per SerDes1 protocols
1005 if (config_serdes1_refclks())
1006 printf("SerDes1 Refclks couldn't set properly.\n");
1008 printf("SerDes1 Refclks have been set.\n");
1010 /* SerDes2 refclks need to be set again, as default clks
1011 * are not suitable for PCIe SATA to work
1012 * This function will set SerDes2's Refclk1 and refclk2
1013 * for SerDes2 protocols having PCIe in them
1014 * for PCIe SATA to work
1016 ret = config_serdes2_refclks();
1018 printf("SerDes2 Refclks have been set.\n");
1019 else if (ret == -ENODEV)
1020 printf("SerDes disable, Refclks couldn't change.\n");
1022 printf("SerDes2 Refclk reconfiguring failed.\n");
1024 #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
1025 defined(CONFIG_SYS_FSL_ERRATUM_A006475)
1026 /* Rechecking the SerDes locks after all SerDes configurations
1027 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
1028 * and at cold temperatures.
1029 * Following sequence ensure the proper locking of SerDes PLLs.
1031 if (SVR_MAJ(get_svr()) == 1) {
1032 if (check_serdes_pll_locks())
1033 printf("SerDes plls still not locked properly.\n");
1035 printf("SerDes plls have been locked well.\n");
1039 /* Configure VSC3316 and VSC3308 crossbar switches */
1040 if (configure_vsc3316_3308())
1041 printf("VSC:failed to configure VSC3316/3308.\n");
1043 printf("VSC:VSC3316/3308 successfully configured.\n");
1045 select_i2c_ch_pca(I2C_CH_DEFAULT);
1050 unsigned long get_board_sys_clk(void)
1052 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
1054 switch ((sysclk_conf & 0x0C) >> 2) {
1065 unsigned long get_board_ddr_clk(void)
1067 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
1069 switch (ddrclk_conf & 0x03) {
1080 static int serdes_refclock(u8 sw, u8 sdclk)
1087 brdcfg4 = QIXIS_READ(brdcfg[4]);
1088 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
1089 return SRDS_PLLCR0_RFCK_SEL_125;
1091 clock = (sw >> 5) & 7;
1093 clock = (sw >> 6) & 3;
1097 ret = SRDS_PLLCR0_RFCK_SEL_100;
1100 ret = SRDS_PLLCR0_RFCK_SEL_125;
1103 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
1106 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
1111 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
1121 #define NUM_SRDS_BANKS 2
1123 int misc_init_r(void)
1126 serdes_corenet_t *srds_regs =
1127 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
1128 u32 actual[NUM_SRDS_BANKS];
1132 sw = QIXIS_READ(brdcfg[2]);
1133 clock = serdes_refclock(sw, 1);
1137 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
1139 sw = QIXIS_READ(brdcfg[4]);
1140 clock = serdes_refclock(sw, 2);
1144 printf("Warning: SDREFCLK2 switch setting unsupported\n");
1146 for (i = 0; i < NUM_SRDS_BANKS; i++) {
1147 u32 pllcr0 = srds_regs->bank[i].pllcr0;
1148 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
1149 if (expected != actual[i]) {
1150 printf("Warning: SERDES bank %u expects reference clock"
1151 " %sMHz, but actual is %sMHz\n", i + 1,
1152 serdes_clock_to_string(expected),
1153 serdes_clock_to_string(actual[i]));
1160 int ft_board_setup(void *blob, bd_t *bd)
1165 ft_cpu_setup(blob, bd);
1167 base = getenv_bootm_low();
1168 size = getenv_bootm_size();
1170 fdt_fixup_memory(blob, (u64)base, (u64)size);
1173 pci_of_setup(blob, bd);
1176 fdt_fixup_liodn(blob);
1178 #ifdef CONFIG_HAS_FSL_DR_USB
1179 fdt_fixup_dr_usb(blob, bd);
1182 #ifdef CONFIG_SYS_DPAA_FMAN
1183 fdt_fixup_fman_ethernet(blob);
1184 fdt_fixup_board_enet(blob);
1191 * Dump board switch settings.
1192 * The bits that cannot be read/sampled via some FPGA or some
1193 * registers, they will be displayed as
1194 * underscore in binary format. mask[] has those bits.
1195 * Some bits are calculated differently than the actual switches
1196 * if booting with overriding by FPGA.
1198 void qixis_dump_switch(void)
1204 * Any bit with 1 means that bit cannot be reverse engineered.
1205 * It will be displayed as _ in binary format.
1207 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
1209 u8 brdcfg[16], dutcfg[16];
1211 for (i = 0; i < 16; i++) {
1212 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
1213 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
1216 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
1218 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
1219 ((dutcfg[2] & 0x07) << 4) | \
1220 ((dutcfg[6] & 0x10) >> 1) | \
1221 ((dutcfg[6] & 0x80) >> 5) | \
1222 ((dutcfg[1] & 0x40) >> 5) | \
1226 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
1227 ((brdcfg[1] & 0xc0) >> 2) | \
1230 puts("DIP switch settings:\n");
1231 for (i = 0; i < 5; i++) {
1232 printf("SW%d = 0b%s (0x%02x)\n",
1233 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);