2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
22 #include "../common/qixis.h"
23 #include "../common/vsc3316_3308.h"
24 #include "../common/idt8t49n222a_serdes_clk.h"
26 #include "b4860qds_qixis.h"
27 #include "b4860qds_crossbar_con.h"
29 #define CLK_MUX_SEL_MASK 0x4
30 #define ETH_PHY_CLK_OUT 0x4
33 DECLARE_GLOBAL_DATA_PTR;
39 struct cpu_type *cpu = gd->arch.cpu;
40 static const char *const freq[] = {"100", "125", "156.25", "161.13",
41 "122.88", "122.88", "122.88"};
44 printf("Board: %sQDS, ", cpu->name);
45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
46 QIXIS_READ(id), QIXIS_READ(arch));
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank: %d\n", sw);
53 else if (sw >= 0x8 && sw <= 0xE)
56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
58 printf("FPGA: v%d (%s), build %d",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor());
61 /* the timestamp string contains "\n" at the end */
62 printf(" on %s", qixis_read_time(buf));
65 * Display the actual SERDES reference clocks as configured by the
66 * dip switches on the board. Note that the SWx registers could
67 * technically be set to force the reference clocks to match the
68 * values that the SERDES expects (or vice versa). For now, however,
69 * we just display both values and hope the user notices when they
72 puts("SERDES Reference Clocks: ");
73 sw = QIXIS_READ(brdcfg[2]);
74 clock = (sw >> 5) & 7;
75 printf("Bank1=%sMHz ", freq[clock]);
76 sw = QIXIS_READ(brdcfg[4]);
77 clock = (sw >> 6) & 3;
78 printf("Bank2=%sMHz\n", freq[clock]);
83 int select_i2c_ch_pca(u8 ch)
87 /* Selecting proper channel via PCA*/
88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
90 printf("PCA: failed to select proper channel.\n");
97 int configure_vsc3316_3308(void)
99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 unsigned int num_vsc16_con, num_vsc08_con;
101 u32 serdes1_prtcl, serdes2_prtcl;
104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
106 if (!serdes1_prtcl) {
107 printf("SERDES1 is not enabled\n");
110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
115 if (!serdes2_prtcl) {
116 printf("SERDES2 is not enabled\n");
119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
122 switch (serdes1_prtcl) {
131 * Lanes: C,D,E,F,G,H: CPRI
133 debug("Configuring crossbar to use onboard SGMII PHYs:"
134 "srds_prctl:%x\n", serdes1_prtcl);
135 num_vsc16_con = NUM_CON_VSC3316;
136 /* Configure VSC3316 crossbar switch */
137 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
139 ret = vsc3316_config(VSC3316_TX_ADDRESS,
140 vsc16_tx_4sfp_sgmii_12_56,
144 ret = vsc3316_config(VSC3316_RX_ADDRESS,
145 vsc16_rx_4sfp_sgmii_12_56,
178 * Lanes: E,F,G,H: CPRI
180 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
181 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
182 num_vsc16_con = NUM_CON_VSC3316;
183 /* Configure VSC3316 crossbar switch */
184 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
186 ret = vsc3316_config(VSC3316_TX_ADDRESS,
187 vsc16_tx_sfp_sgmii_aurora,
191 ret = vsc3316_config(VSC3316_RX_ADDRESS,
192 vsc16_rx_sfp_sgmii_aurora,
201 #ifdef CONFIG_PPC_B4420
206 * Lanes: A,B,C,D: SGMII
207 * Lanes: E,F,G,H: CPRI
209 debug("Configuring crossbar to use onboard SGMII PHYs:"
210 "srds_prctl:%x\n", serdes1_prtcl);
211 num_vsc16_con = NUM_CON_VSC3316;
212 /* Configure VSC3316 crossbar switch */
213 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
215 ret = vsc3316_config(VSC3316_TX_ADDRESS,
216 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
219 ret = vsc3316_config(VSC3316_RX_ADDRESS,
220 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
233 num_vsc16_con = NUM_CON_VSC3316;
234 /* Configure VSC3316 crossbar switch */
235 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
237 ret = vsc3316_config(VSC3316_TX_ADDRESS,
238 vsc16_tx_sfp, num_vsc16_con);
241 ret = vsc3316_config(VSC3316_RX_ADDRESS,
242 vsc16_rx_sfp, num_vsc16_con);
250 printf("WARNING:VSC crossbars programming not supported for:%x"
251 " SerDes1 Protocol.\n", serdes1_prtcl);
255 switch (serdes2_prtcl) {
264 num_vsc08_con = NUM_CON_VSC3308;
265 /* Configure VSC3308 crossbar switch */
266 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
268 ret = vsc3308_config(VSC3308_TX_ADDRESS,
269 vsc08_tx_amc, num_vsc08_con);
272 ret = vsc3308_config(VSC3308_RX_ADDRESS,
273 vsc08_rx_amc, num_vsc08_con);
281 printf("WARNING:VSC crossbars programming not supported for: %x"
282 " SerDes2 Protocol.\n", serdes2_prtcl);
289 int config_serdes1_refclks(void)
291 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
292 serdes_corenet_t *srds_regs =
293 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
294 u32 serdes1_prtcl, lane;
295 unsigned int flag_sgmii_aurora_prtcl = 0;
298 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
299 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
300 if (!serdes1_prtcl) {
301 printf("SERDES1 is not enabled\n");
304 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
305 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
307 /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
309 for (i = 0; i < PLL_NUM; i++)
310 clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
311 /* Reconfigure IDT idt8t49n222a device for CPRI to work
312 * For this SerDes1's Refclk1 and refclk2 need to be set
315 switch (serdes1_prtcl) {
339 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
340 " for srds_prctl:%x\n", serdes1_prtcl);
341 ret = select_i2c_ch_pca(I2C_CH_IDT);
343 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
344 SERDES_REFCLK_122_88,
345 SERDES_REFCLK_122_88, 0);
347 printf("IDT8T49N222A configuration failed.\n");
350 printf("IDT8T49N222A configured.\n");
354 select_i2c_ch_pca(I2C_CH_DEFAULT);
356 /* Change SerDes1's Refclk1 to 125MHz for on board
357 * SGMIIs or Aurora to work
359 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
360 enum srds_prtcl lane_prtcl = serdes_get_prtcl
361 (0, serdes1_prtcl, lane);
362 switch (lane_prtcl) {
363 case SGMII_FM1_DTSEC1:
364 case SGMII_FM1_DTSEC2:
365 case SGMII_FM1_DTSEC3:
366 case SGMII_FM1_DTSEC4:
367 case SGMII_FM1_DTSEC5:
368 case SGMII_FM1_DTSEC6:
370 flag_sgmii_aurora_prtcl++;
377 if (flag_sgmii_aurora_prtcl)
378 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
380 /* Steps For SerDes PLLs reset and reconfiguration after
381 * changing SerDes's refclks
383 for (i = 0; i < PLL_NUM; i++) {
384 debug("For PLL%d reset and reconfiguration after"
385 " changing refclks\n", i+1);
386 clrbits_be32(&srds_regs->bank[i].rstctl,
387 SRDS_RSTCTL_SDRST_B);
389 clrbits_be32(&srds_regs->bank[i].rstctl,
390 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
392 setbits_be32(&srds_regs->bank[i].rstctl,
394 setbits_be32(&srds_regs->bank[i].rstctl,
395 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
396 | SRDS_RSTCTL_SDRST_B));
400 printf("WARNING:IDT8T49N222A configuration not"
401 " supported for:%x SerDes1 Protocol.\n",
409 int board_early_init_r(void)
411 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
412 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
415 * Remap Boot flash + PROMJET region to caching-inhibited
416 * so that flash can be erased properly.
419 /* Flush d-cache and invalidate i-cache of any FLASH data */
423 /* invalidate existing TLB entry for flash + promjet */
424 disable_tlb(flash_esel);
426 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
427 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
428 0, flash_esel, BOOKE_PAGESZ_256M, 1);
431 #ifdef CONFIG_SYS_DPAA_QBMAN
434 /* SerDes1 refclks need to be set again, as default clks
435 * are not suitable for CPRI and onboard SGMIIs to work
437 * This function will set SerDes1's Refclk1 and refclk2
438 * as per SerDes1 protocols
440 if (config_serdes1_refclks())
441 printf("SerDes1 Refclks couldn't set properly.\n");
443 printf("SerDes1 Refclks have been set.\n");
445 /* Configure VSC3316 and VSC3308 crossbar switches */
446 if (configure_vsc3316_3308())
447 printf("VSC:failed to configure VSC3316/3308.\n");
449 printf("VSC:VSC3316/3308 successfully configured.\n");
451 select_i2c_ch_pca(I2C_CH_DEFAULT);
456 unsigned long get_board_sys_clk(void)
458 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
460 switch ((sysclk_conf & 0x0C) >> 2) {
471 unsigned long get_board_ddr_clk(void)
473 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
475 switch (ddrclk_conf & 0x03) {
486 static int serdes_refclock(u8 sw, u8 sdclk)
493 brdcfg4 = QIXIS_READ(brdcfg[4]);
494 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
495 return SRDS_PLLCR0_RFCK_SEL_125;
497 clock = (sw >> 5) & 7;
499 clock = (sw >> 6) & 3;
503 ret = SRDS_PLLCR0_RFCK_SEL_100;
506 ret = SRDS_PLLCR0_RFCK_SEL_125;
509 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
512 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
517 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
527 #define NUM_SRDS_BANKS 2
529 int misc_init_r(void)
532 serdes_corenet_t *srds_regs =
533 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
534 u32 actual[NUM_SRDS_BANKS];
538 sw = QIXIS_READ(brdcfg[2]);
539 clock = serdes_refclock(sw, 1);
543 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
545 sw = QIXIS_READ(brdcfg[4]);
546 clock = serdes_refclock(sw, 2);
550 printf("Warning: SDREFCLK2 switch setting unsupported\n");
552 for (i = 0; i < NUM_SRDS_BANKS; i++) {
553 u32 pllcr0 = srds_regs->bank[i].pllcr0;
554 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
555 if (expected != actual[i]) {
556 printf("Warning: SERDES bank %u expects reference clock"
557 " %sMHz, but actual is %sMHz\n", i + 1,
558 serdes_clock_to_string(expected),
559 serdes_clock_to_string(actual[i]));
566 void ft_board_setup(void *blob, bd_t *bd)
571 ft_cpu_setup(blob, bd);
573 base = getenv_bootm_low();
574 size = getenv_bootm_size();
576 fdt_fixup_memory(blob, (u64)base, (u64)size);
579 pci_of_setup(blob, bd);
582 fdt_fixup_liodn(blob);
584 #ifdef CONFIG_HAS_FSL_DR_USB
585 fdt_fixup_dr_usb(blob, bd);
588 #ifdef CONFIG_SYS_DPAA_FMAN
589 fdt_fixup_fman_ethernet(blob);
590 fdt_fixup_board_enet(blob);
595 * Dump board switch settings.
596 * The bits that cannot be read/sampled via some FPGA or some
597 * registers, they will be displayed as
598 * underscore in binary format. mask[] has those bits.
599 * Some bits are calculated differently than the actual switches
600 * if booting with overriding by FPGA.
602 void qixis_dump_switch(void)
608 * Any bit with 1 means that bit cannot be reverse engineered.
609 * It will be displayed as _ in binary format.
611 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
613 u8 brdcfg[16], dutcfg[16];
615 for (i = 0; i < 16; i++) {
616 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
617 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
620 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
622 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
623 ((dutcfg[2] & 0x07) << 4) | \
624 ((dutcfg[6] & 0x10) >> 1) | \
625 ((dutcfg[6] & 0x80) >> 5) | \
626 ((dutcfg[1] & 0x40) >> 5) | \
630 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
631 ((brdcfg[1] & 0xc0) >> 2) | \
634 puts("DIP switch settings:\n");
635 for (i = 0; i < 5; i++) {
636 printf("SW%d = 0b%s (0x%02x)\n",
637 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);