2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/processor.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
15 #include <fdt_support.h>
20 #include <asm/fsl_ifc.h>
23 #include <asm/fsl_ddr_sdram.h>
27 #include <asm/fsl_pci.h>
30 #include "../common/qixis.h"
31 DECLARE_GLOBAL_DATA_PTR;
34 int board_early_init_f(void)
36 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
38 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
43 void board_config_serdes_mux(void)
45 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
46 u32 pordevsr = in_be32(&gur->pordevsr);
47 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
48 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
51 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
62 QIXIS_WRITE_I2C(brdcfg[4], 0x03);
65 /* PEX(1) PEX(2) SGMII1 CPRI 1 */
76 QIXIS_WRITE_I2C(brdcfg[4], 0x01);
79 /* PEX(1) PEX(2) SGMII1 SGMII2 */
82 QIXIS_WRITE_I2C(brdcfg[4], 0x00);
85 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
96 QIXIS_WRITE_I2C(brdcfg[4], 0x07);
99 /* PEX(1) SGMII2 SGMII1 CPRI 1 */
110 QIXIS_WRITE_I2C(brdcfg[4], 0x05);
113 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
119 QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
128 int board_early_init_r(void)
130 #ifndef CONFIG_SYS_NO_FLASH
131 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
132 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
135 * Remap Boot flash region to caching-inhibited
136 * so that flash can be erased properly.
139 /* Flush d-cache and invalidate i-cache of any FLASH data */
143 /* invalidate existing TLB entry for flash */
144 disable_tlb(flash_esel);
146 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
147 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
148 0, flash_esel, BOOKE_PAGESZ_64M, 1);
150 set_tlb(1, flashbase + 0x4000000,
151 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
152 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
153 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
155 board_config_serdes_mux();
160 void pci_init_board(void)
162 fsl_pcie_init_board(0);
164 #endif /* ifdef CONFIG_PCI */
168 struct cpu_type *cpu;
172 printf("Board: %sQDS\n", cpu->name);
174 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
175 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
177 sw = QIXIS_READ(brdcfg[0]);
178 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
180 printf("IFC chip select:");
192 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
199 #ifdef CONFIG_TSEC_ENET
200 int board_eth_init(bd_t *bis)
202 struct fsl_pq_mdio_info mdio_info;
203 struct tsec_info_struct tsec_info[4];
207 SET_STD_TSEC_INFO(tsec_info[num], 1);
213 SET_STD_TSEC_INFO(tsec_info[num], 2);
217 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
218 mdio_info.name = DEFAULT_MII_NAME;
220 fsl_pq_mdio_init(bis, &mdio_info);
221 tsec_eth_init(bis, tsec_info, num);
231 #define USBMUX_SEL_MASK 0xc0
232 #define USBMUX_SEL_UART2 0xc0
233 #define USBMUX_SEL_USB 0x40
234 #define SPIMUX_SEL_UART3 0x80
235 #define GPS_MUX_SEL_GPS 0x40
237 #define TSEC_1588_CLKIN_MASK 0x03
238 #define CON_XCVR_REF_CLK 0x00
240 int misc_init_r(void)
243 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
244 u32 porbmsr = in_be32(&gur->porbmsr);
245 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
247 /*Configure 1588 clock-in source from RF Card*/
248 val = QIXIS_READ_I2C(brdcfg[5]);
249 QIXIS_WRITE_I2C(brdcfg[5],
250 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
252 if (hwconfig("uart2") && hwconfig("usb1")) {
253 printf("UART2 and USB cannot work together on the board\n");
254 printf("Remove one from hwconfig and reset\n");
256 if (hwconfig("uart2")) {
257 val = QIXIS_READ_I2C(brdcfg[5]);
258 QIXIS_WRITE_I2C(brdcfg[5],
259 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
260 clrbits_be32(&gur->pmuxcr3,
261 MPC85xx_PMUXCR3_USB_SEL_MASK);
262 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
264 /* By default USB should be selected.
265 * Programming FPGA to select USB. */
266 val = QIXIS_READ_I2C(brdcfg[5]);
267 QIXIS_WRITE_I2C(brdcfg[5],
268 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
273 if (hwconfig("sim")) {
274 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
275 romloc == PORBMSR_ROMLOC_NOR ||
276 romloc == PORBMSR_ROMLOC_SPI) {
278 val = QIXIS_READ_I2C(brdcfg[3]);
279 QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
280 clrbits_be32(&gur->pmuxcr,
281 MPC85xx_PMUXCR0_SIM_SEL_MASK);
282 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
286 if (hwconfig("uart3")) {
287 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
288 romloc == PORBMSR_ROMLOC_NOR ||
289 romloc == PORBMSR_ROMLOC_SDHC) {
291 /* UART3 and SPI1 (Flashes) are muxed together */
292 val = QIXIS_READ_I2C(brdcfg[3]);
293 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
294 clrbits_be32(&gur->pmuxcr3,
295 MPC85xx_PMUXCR3_UART3_SEL_MASK);
296 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
298 /* MUX to select UART3 connection to J24 header
300 val = QIXIS_READ_I2C(brdcfg[6]);
302 QIXIS_WRITE_I2C(brdcfg[6],
303 (val | GPS_MUX_SEL_GPS));
305 QIXIS_WRITE_I2C(brdcfg[6],
306 (val & ~(GPS_MUX_SEL_GPS)));
312 void fdt_del_node_compat(void *blob, const char *compatible)
315 int off = fdt_node_offset_by_compatible(blob, -1, compatible);
317 printf("WARNING: could not find compatible node %s: %s.\n",
318 compatible, fdt_strerror(off));
321 err = fdt_del_node(blob, off);
323 printf("WARNING: could not remove %s: %s.\n",
324 compatible, fdt_strerror(err));
328 #if defined(CONFIG_OF_BOARD_SETUP)
329 void ft_board_setup(void *blob, bd_t *bd)
334 ft_cpu_setup(blob, bd);
336 base = getenv_bootm_low();
337 size = getenv_bootm_size();
339 #if defined(CONFIG_PCI)
343 fdt_fixup_memory(blob, (u64)base, (u64)size);
345 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
346 u32 porbmsr = in_be32(&gur->porbmsr);
347 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
349 if (!(hwconfig("uart2") && hwconfig("usb1"))) {
350 /* If uart2 is there in hwconfig remove usb node from
353 if (hwconfig("uart2")) {
354 /* remove dts usb node */
355 fdt_del_node_compat(blob, "fsl-usb2-dr");
357 fdt_fixup_dr_usb(blob, bd);
358 fdt_del_node_and_alias(blob, "serial2");
362 if (hwconfig("uart3")) {
363 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
364 romloc == PORBMSR_ROMLOC_NOR ||
365 romloc == PORBMSR_ROMLOC_SDHC)
366 /* Delete SPI node from the device tree */
367 fdt_del_node_and_alias(blob, "spi1");
369 fdt_del_node_and_alias(blob, "serial3");
371 if (hwconfig("sim")) {
372 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
373 romloc == PORBMSR_ROMLOC_NOR ||
374 romloc == PORBMSR_ROMLOC_SPI) {
376 /* remove dts sdhc node */
377 fdt_del_node_compat(blob, "fsl,esdhc");
378 } else if (romloc == PORBMSR_ROMLOC_SDHC) {
380 /* remove dts sim node */
381 fdt_del_node_compat(blob, "fsl,sim-v1.0");
382 printf("SIM & SDHC can't work together on the board");
383 printf("\nRemove sim from hwconfig and reset\n");