2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
34 static ulong strfractoint(uchar *strptr);
40 void pixis_reset(void)
42 out8(PIXIS_BASE + PIXIS_RST, 0);
47 * Per table 27, page 58 of MPC8641HPCN spec.
49 int set_px_sysclk(ulong sysclk)
51 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
103 printf("Unsupported SYSCLK frequency.\n");
107 vclkh = (sysclk_s << 5) | sysclk_r;
110 out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
111 out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
113 out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
119 int set_px_mpxpll(ulong mpxpll)
136 printf("Unsupported MPXPLL ratio.\n");
140 tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
141 tmp = (tmp & 0xF0) | (val & 0x0F);
142 out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
148 int set_px_corepll(ulong corepll)
153 switch ((int)corepll) {
173 printf("Unsupported COREPLL ratio.\n");
177 tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
178 tmp = (tmp & 0xE0) | (val & 0x1F);
179 out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
185 void read_from_px_regs(int set)
187 u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
188 u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
194 out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
198 void read_from_px_regs_altbank(int set)
200 u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
201 u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
207 out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
210 #ifndef CFG_PIXIS_VBOOT_MASK
211 #define CFG_PIXIS_VBOOT_MASK (0x40)
214 void clear_altbank(void)
218 tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
219 tmp &= ~CFG_PIXIS_VBOOT_MASK;
221 out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
225 void set_altbank(void)
229 tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
230 tmp |= CFG_PIXIS_VBOOT_MASK;
232 out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
240 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
241 tmp = tmp & 0x1E; /* clear GO bit */
242 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
244 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
245 tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
246 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
250 void set_px_go_with_watchdog(void)
254 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
256 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
258 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
260 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
264 int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
265 int flag, int argc, char *argv[])
269 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
271 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
273 /* setting VCTL[WDEN] to 0 to disable watch dog */
274 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
276 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
282 diswd, 1, 0, pixis_disable_watchdog_cmd,
283 "diswd - Disable watchdog timer \n",
286 #ifdef CONFIG_FSL_SGMII_RISER
287 int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
294 if (strcmp(argv[1], "all") != 0)
295 which_tsec = simple_strtoul(argv[1], NULL, 0);
297 switch (which_tsec) {
299 mask = PIXIS_VSPEED2_TSEC1SER;
300 switch_mask = PIXIS_VCFGEN1_TSEC1SER;
303 mask = PIXIS_VSPEED2_TSEC3SER;
304 switch_mask = PIXIS_VCFGEN1_TSEC3SER;
307 mask = PIXIS_VSPEED2_TSEC1SER | PIXIS_VSPEED2_TSEC3SER;
308 switch_mask = PIXIS_VCFGEN1_TSEC1SER | PIXIS_VCFGEN1_TSEC3SER;
312 /* Toggle whether the switches or FPGA control the settings */
313 if (!strcmp(argv[argc - 1], "switch"))
314 clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
317 setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
320 /* If it's not the switches, enable or disable SGMII, as specified */
321 if (!strcmp(argv[argc - 1], "on"))
322 clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
323 else if (!strcmp(argv[argc - 1], "off"))
324 setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
330 pixis_set_sgmii, CFG_MAXARGS, 1, pixis_set_sgmii,
332 " - Enable or disable SGMII mode for a given TSEC \n",
333 "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
334 " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
335 " on - enables SGMII\n"
336 " off - disables SGMII\n"
337 " switch - use switch settings\n");
341 * This function takes the non-integral cpu:mpx pll ratio
342 * and converts it to an integer that can be used to assign
343 * FPGA register values.
344 * input: strptr i.e. argv[2]
347 static ulong strfractoint(uchar *strptr)
351 int intarr_len = 0, decarr_len = 0, no_dec = 0;
352 ulong intval = 0, decval = 0;
353 uchar intarr[3], decarr[3];
355 /* Assign the integer part to intarr[]
356 * If there is no decimal point i.e.
357 * if the ratio is an integral value
358 * simply create the intarr.
361 while (strptr[i] != '.') {
362 if (strptr[i] == 0) {
366 intarr[i] = strptr[i];
370 /* Assign length of integer part to intarr_len. */
375 /* Currently needed only for single digit corepll ratios */
380 i++; /* Skipping the decimal point */
381 while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
382 decarr[j] = strptr[i];
391 for (i = 0; i < decarr_len; i++)
393 decval = simple_strtoul((char *)decarr, NULL, 10);
396 intval = simple_strtoul((char *)intarr, NULL, 10);
397 intval = intval * mulconst;
399 retval = intval + decval;
406 pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
410 char *p_cf_sysclk = NULL;
411 char *p_cf_corepll = NULL;
412 char *p_cf_mpxpll = NULL;
413 char *p_altbank = NULL;
415 unsigned int unknown_param = 0;
418 * No args is a simple reset request.
425 for (i = 1; i < argc; i++) {
426 if (strcmp(argv[i], "cf") == 0) {
431 p_cf_sysclk = argv[i+1];
432 p_cf_corepll = argv[i+2];
433 p_cf_mpxpll = argv[i+3];
438 if (strcmp(argv[i], "altbank") == 0) {
443 if (strcmp(argv[i], "wd") == 0) {
452 * Check that cf has all required parms
454 if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
461 * PIXIS seems to be sensitive to the ordering of
462 * the registers that are touched.
464 read_from_px_regs(0);
467 read_from_px_regs_altbank(0);
472 * Clock configuration specified.
475 unsigned long sysclk;
476 unsigned long corepll;
477 unsigned long mpxpll;
479 sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
480 corepll = strfractoint((uchar *) p_cf_corepll);
481 mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
483 if (!(set_px_sysclk(sysclk)
484 && set_px_corepll(corepll)
485 && set_px_mpxpll(mpxpll))) {
489 read_from_px_regs(1);
495 * NOTE CHANGE IN BEHAVIOR: previous code would default
496 * to enabling watchdog if altbank is specified.
497 * Now the watchdog must be enabled explicitly using 'wd'.
501 read_from_px_regs_altbank(1);
505 * Reset with watchdog specified.
508 set_px_go_with_watchdog();
514 * Shouldn't be reached.
521 pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
522 "pixis_reset - Reset the board using the FPGA sequencer\n",
524 " pixis_reset [altbank]\n"
525 " pixis_reset altbank wd\n"
526 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
527 " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"