2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
20 #include <fsl_esdhc.h>
25 #include "../common/qixis.h"
26 #include "ls1012aqds_qixis.h"
28 DECLARE_GLOBAL_DATA_PTR;
35 sw = QIXIS_READ(arch);
36 printf("Board Arch: V%d, ", sw >> 4);
37 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
39 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
41 if (sw & QIXIS_LBMAP_ALTBANK)
46 printf("FPGA: v%d (%s), build %d",
47 (int)QIXIS_READ(scver), qixis_read_tag(buf),
48 (int)qixis_read_minor());
50 /* the timestamp string contains "\n" at the end */
51 printf(" on %s", qixis_read_time(buf));
59 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
64 int board_early_init_f(void)
66 fsl_lsch2_early_init_f();
71 #ifdef CONFIG_MISC_INIT_R
74 u8 mux_sdhc_cd = 0x80;
78 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
85 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
86 CONFIG_SYS_CCI400_ADDR;
88 /* Set CCI-400 control override register to enable barrier
90 out_le32(&cci->ctrl_ord,
91 CCI400_CTRLORD_EN_BARRIER);
93 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
97 #ifdef CONFIG_ENV_IS_NOWHERE
98 gd->env_addr = (ulong)&default_environment[0];
103 int board_eth_init(bd_t *bis)
105 return pci_eth_init(bis);
108 #ifdef CONFIG_OF_BOARD_SETUP
109 int ft_board_setup(void *blob, bd_t *bd)
111 arch_fixup_fdt(blob);
113 ft_cpu_setup(blob, bd);