board/freescale/ls1021aqds/ls1021aqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <asm/pcie_layerscape.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <fsl_ifc.h>
  20 #include <fsl_sec.h>
  21 #include <spl.h>
  22
  23 #include "../common/qixis.h"
  24 #include "ls1021aqds_qixis.h"
  25 #ifdef CONFIG_U_QE
  26 #include "../../../drivers/qe/qe.h"
  27 #endif
  28
  29 #define PIN_MUX_SEL_CAN         0x03
  30 #define PIN_MUX_SEL_IIC2        0xa0
  31 #define PIN_MUX_SEL_RGMII       0x00
  32 #define PIN_MUX_SEL_SAI         0x0c
  33 #define PIN_MUX_SEL_SDHC        0x00
  34
  35 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0x0f) | value)
  36 #define SET_EC_MUX_SEL(reg, value)      ((reg & 0xf0) | value)
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         MUX_TYPE_CAN,
  41         MUX_TYPE_IIC2,
  42         MUX_TYPE_RGMII,
  43         MUX_TYPE_SAI,
  44         MUX_TYPE_SDHC,
  45         MUX_TYPE_SD_PCI4,
  46         MUX_TYPE_SD_PC_SA_SG_SG,
  47         MUX_TYPE_SD_PC_SA_PC_SG,
  48         MUX_TYPE_SD_PC_SG_SG,
  49 };
  50
  51 enum {
  52         GE0_CLK125,
  53         GE2_CLK125,
  54         GE1_CLK125,
  55 };
  56
  57 int checkboard(void)
  58 {
  59 #ifndef CONFIG_QSPI_BOOT
  60         char buf[64];
  61 #endif
  62 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  63         u8 sw;
  64 #endif
  65
  66         puts("Board: LS1021AQDS\n");
  67
  68 #ifdef CONFIG_SD_BOOT
  69         puts("SD\n");
  70 #elif CONFIG_QSPI_BOOT
  71         puts("QSPI\n");
  72 #else
  73         sw = QIXIS_READ(brdcfg[0]);
  74         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  75
  76         if (sw < 0x8)
  77                 printf("vBank: %d\n", sw);
  78         else if (sw == 0x8)
  79                 puts("PromJet\n");
  80         else if (sw == 0x9)
  81                 puts("NAND\n");
  82         else if (sw == 0x15)
  83                 printf("IFCCard\n");
  84         else
  85                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  86 #endif
  87
  88 #ifndef CONFIG_QSPI_BOOT
  89         printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  90                QIXIS_READ(id), QIXIS_READ(arch));
  91
  92         printf("FPGA:  v%d (%s), build %d\n",
  93                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  94                (int)qixis_read_minor());
  95 #endif
  96
  97         return 0;
  98 }
  99
 100 unsigned long get_board_sys_clk(void)
 101 {
 102         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 103
 104         switch (sysclk_conf & 0x0f) {
 105         case QIXIS_SYSCLK_64:
 106                 return 64000000;
 107         case QIXIS_SYSCLK_83:
 108                 return 83333333;
 109         case QIXIS_SYSCLK_100:
 110                 return 100000000;
 111         case QIXIS_SYSCLK_125:
 112                 return 125000000;
 113         case QIXIS_SYSCLK_133:
 114                 return 133333333;
 115         case QIXIS_SYSCLK_150:
 116                 return 150000000;
 117         case QIXIS_SYSCLK_160:
 118                 return 160000000;
 119         case QIXIS_SYSCLK_166:
 120                 return 166666666;
 121         }
 122         return 66666666;
 123 }
 124
 125 unsigned long get_board_ddr_clk(void)
 126 {
 127         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 128
 129         switch ((ddrclk_conf & 0x30) >> 4) {
 130         case QIXIS_DDRCLK_100:
 131                 return 100000000;
 132         case QIXIS_DDRCLK_125:
 133                 return 125000000;
 134         case QIXIS_DDRCLK_133:
 135                 return 133333333;
 136         }
 137         return 66666666;
 138 }
 139
 140 int select_i2c_ch_pca9547(u8 ch)
 141 {
 142         int ret;
 143
 144         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 145         if (ret) {
 146                 puts("PCA: failed to select proper channel\n");
 147                 return ret;
 148         }
 149
 150         return 0;
 151 }
 152
 153 int dram_init(void)
 154 {
 155         /*
 156          * When resuming from deep sleep, the I2C channel may not be
 157          * in the default channel. So, switch to the default channel
 158          * before accessing DDR SPD.
 159          */
 160         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 161         gd->ram_size = initdram(0);
 162
 163         return 0;
 164 }
 165
 166 #ifdef CONFIG_FSL_ESDHC
 167 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 168         {CONFIG_SYS_FSL_ESDHC_ADDR},
 169 };
 170
 171 int board_mmc_init(bd_t *bis)
 172 {
 173         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 174
 175         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 176 }
 177 #endif
 178
 179 int board_early_init_f(void)
 180 {
 181         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 182         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 183
 184 #ifdef CONFIG_TSEC_ENET
 185         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 186 #endif
 187
 188 #ifdef CONFIG_FSL_IFC
 189         init_early_memctl_regs();
 190 #endif
 191
 192 #ifdef CONFIG_FSL_QSPI
 193         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 194 #endif
 195
 196 #ifdef CONFIG_FSL_DCU_FB
 197         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 198 #endif
 199
 200         /*
 201          * Enable snoop requests and DVM message requests for
 202          * Slave insterface S4 (A7 core cluster)
 203          */
 204         out_le32(&cci->slave[4].snoop_ctrl,
 205                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 206
 207         /*
 208          * Set CCI-400 Slave interface S1, S2 Shareable Override Register
 209          * All transactions are treated as non-shareable
 210          */
 211         out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 212         out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 213
 214         /* Workaround for the issue that DDR could not respond to
 215          * barrier transaction which is generated by executing DSB/ISB
 216          * instruction. Set CCI-400 control override register to
 217          * terminate the barrier transaction. After DDR is initialized,
 218          * allow barrier transaction to DDR again */
 219         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 220
 221         return 0;
 222 }
 223
 224 #ifdef CONFIG_SPL_BUILD
 225 void board_init_f(ulong dummy)
 226 {
 227         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 228
 229 #ifdef CONFIG_NAND_BOOT
 230         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 231         u32 porsr1, pinctl;
 232
 233         /*
 234          * There is LS1 SoC issue where NOR, FPGA are inaccessible during
 235          * NAND boot because IFC signals > IFC_AD7 are not enabled.
 236          * This workaround changes RCW source to make all signals enabled.
 237          */
 238         porsr1 = in_be32(&gur->porsr1);
 239         pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 240                  DCFG_CCSR_PORSR1_RCW_SRC_I2C);
 241         out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 242                  pinctl);
 243 #endif
 244
 245         /* Clear the BSS */
 246         memset(__bss_start, 0, __bss_end - __bss_start);
 247
 248 #ifdef CONFIG_FSL_IFC
 249         init_early_memctl_regs();
 250 #endif
 251
 252         get_clocks();
 253
 254         preloader_console_init();
 255
 256 #ifdef CONFIG_SPL_I2C_SUPPORT
 257         i2c_init_all();
 258 #endif
 259         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 260
 261         dram_init();
 262
 263         board_init_r(NULL, 0);
 264 }
 265 #endif
 266
 267 void config_etseccm_source(int etsec_gtx_125_mux)
 268 {
 269         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 270
 271         switch (etsec_gtx_125_mux) {
 272         case GE0_CLK125:
 273                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
 274                 debug("etseccm set to GE0_CLK125\n");
 275                 break;
 276
 277         case GE2_CLK125:
 278                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 279                 debug("etseccm set to GE2_CLK125\n");
 280                 break;
 281
 282         case GE1_CLK125:
 283                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
 284                 debug("etseccm set to GE1_CLK125\n");
 285                 break;
 286
 287         default:
 288                 printf("Error! trying to set etseccm to invalid value\n");
 289                 break;
 290         }
 291 }
 292
 293 int config_board_mux(int ctrl_type)
 294 {
 295         u8 reg12, reg14;
 296
 297         reg12 = QIXIS_READ(brdcfg[12]);
 298         reg14 = QIXIS_READ(brdcfg[14]);
 299
 300         switch (ctrl_type) {
 301         case MUX_TYPE_CAN:
 302                 config_etseccm_source(GE2_CLK125);
 303                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
 304                 break;
 305         case MUX_TYPE_IIC2:
 306                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
 307                 break;
 308         case MUX_TYPE_RGMII:
 309                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
 310                 break;
 311         case MUX_TYPE_SAI:
 312                 config_etseccm_source(GE2_CLK125);
 313                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
 314                 break;
 315         case MUX_TYPE_SDHC:
 316                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
 317                 break;
 318         case MUX_TYPE_SD_PCI4:
 319                 reg12 = 0x38;
 320                 break;
 321         case MUX_TYPE_SD_PC_SA_SG_SG:
 322                 reg12 = 0x01;
 323                 break;
 324         case MUX_TYPE_SD_PC_SA_PC_SG:
 325                 reg12 = 0x01;
 326                 break;
 327         case MUX_TYPE_SD_PC_SG_SG:
 328                 reg12 = 0x21;
 329                 break;
 330         default:
 331                 printf("Wrong mux interface type\n");
 332                 return -1;
 333         }
 334
 335         QIXIS_WRITE(brdcfg[12], reg12);
 336         QIXIS_WRITE(brdcfg[14], reg14);
 337
 338         return 0;
 339 }
 340
 341 int config_serdes_mux(void)
 342 {
 343         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
 344         u32 cfg;
 345
 346         cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 347         cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 348
 349         switch (cfg) {
 350         case 0x0:
 351                 config_board_mux(MUX_TYPE_SD_PCI4);
 352                 break;
 353         case 0x30:
 354                 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
 355                 break;
 356         case 0x60:
 357                 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
 358                 break;
 359         case 0x70:
 360                 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
 361                 break;
 362         default:
 363                 printf("SRDS1 prtcl:0x%x\n", cfg);
 364                 break;
 365         }
 366
 367         return 0;
 368 }
 369
 370 int misc_init_r(void)
 371 {
 372         int conflict_flag;
 373
 374         /* some signals can not enable simultaneous*/
 375         conflict_flag = 0;
 376         if (hwconfig("sdhc"))
 377                 conflict_flag++;
 378         if (hwconfig("iic2"))
 379                 conflict_flag++;
 380         if (conflict_flag > 1) {
 381                 printf("WARNING: pin conflict !\n");
 382                 return 0;
 383         }
 384
 385         conflict_flag = 0;
 386         if (hwconfig("rgmii"))
 387                 conflict_flag++;
 388         if (hwconfig("can"))
 389                 conflict_flag++;
 390         if (hwconfig("sai"))
 391                 conflict_flag++;
 392         if (conflict_flag > 1) {
 393                 printf("WARNING: pin conflict !\n");
 394                 return 0;
 395         }
 396
 397         if (hwconfig("can"))
 398                 config_board_mux(MUX_TYPE_CAN);
 399         else if (hwconfig("rgmii"))
 400                 config_board_mux(MUX_TYPE_RGMII);
 401         else if (hwconfig("sai"))
 402                 config_board_mux(MUX_TYPE_SAI);
 403
 404         if (hwconfig("iic2"))
 405                 config_board_mux(MUX_TYPE_IIC2);
 406         else if (hwconfig("sdhc"))
 407                 config_board_mux(MUX_TYPE_SDHC);
 408
 409 #ifdef CONFIG_FSL_CAAM
 410         return sec_init();
 411 #endif
 412         return 0;
 413 }
 414
 415 #ifdef CONFIG_LS102XA_NS_ACCESS
 416 static struct csu_ns_dev ns_dev[] = {
 417         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 418         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 419         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 420         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 421         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 422         { CSU_CSLX_GIC, CSU_ALL_RW },
 423         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 424         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 425         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 426         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 427         { CSU_CSLX_SATA, CSU_ALL_RW },
 428         { CSU_CSLX_USB3, CSU_ALL_RW },
 429         { CSU_CSLX_SERDES, CSU_ALL_RW },
 430         { CSU_CSLX_QDMA, CSU_ALL_RW },
 431         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 432         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 433         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 434         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 435         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 436         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 437         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 438         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 439         { CSU_CSLX_QSPI, CSU_ALL_RW },
 440         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 441         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 442         { CSU_CSLX_IFC, CSU_ALL_RW },
 443         { CSU_CSLX_I2C1, CSU_ALL_RW },
 444         { CSU_CSLX_USB2, CSU_ALL_RW },
 445         { CSU_CSLX_I2C3, CSU_ALL_RW },
 446         { CSU_CSLX_I2C2, CSU_ALL_RW },
 447         { CSU_CSLX_DUART2, CSU_ALL_RW },
 448         { CSU_CSLX_DUART1, CSU_ALL_RW },
 449         { CSU_CSLX_WDT2, CSU_ALL_RW },
 450         { CSU_CSLX_WDT1, CSU_ALL_RW },
 451         { CSU_CSLX_EDMA, CSU_ALL_RW },
 452         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 453         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 454         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 455         { CSU_CSLX_DDR, CSU_ALL_RW },
 456         { CSU_CSLX_QUICC, CSU_ALL_RW },
 457         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 458         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 459         { CSU_CSLX_SFP, CSU_ALL_RW },
 460         { CSU_CSLX_TMU, CSU_ALL_RW },
 461         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 462         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 463         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 464         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 465         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 466         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 467         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 468         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 469         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 470         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 471         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 472         { CSU_CSLX_CSU, CSU_ALL_RW },
 473         { CSU_CSLX_ASRC, CSU_ALL_RW },
 474         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 475         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 476         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 477         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 478         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 479         { CSU_CSLX_SAI2, CSU_ALL_RW },
 480         { CSU_CSLX_SAI1, CSU_ALL_RW },
 481         { CSU_CSLX_SAI4, CSU_ALL_RW },
 482         { CSU_CSLX_SAI3, CSU_ALL_RW },
 483         { CSU_CSLX_FTM2, CSU_ALL_RW },
 484         { CSU_CSLX_FTM1, CSU_ALL_RW },
 485         { CSU_CSLX_FTM4, CSU_ALL_RW },
 486         { CSU_CSLX_FTM3, CSU_ALL_RW },
 487         { CSU_CSLX_FTM6, CSU_ALL_RW },
 488         { CSU_CSLX_FTM5, CSU_ALL_RW },
 489         { CSU_CSLX_FTM8, CSU_ALL_RW },
 490         { CSU_CSLX_FTM7, CSU_ALL_RW },
 491         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 492         { CSU_CSLX_EPU, CSU_ALL_RW },
 493         { CSU_CSLX_GDI, CSU_ALL_RW },
 494         { CSU_CSLX_DDI, CSU_ALL_RW },
 495         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 496         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 497         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 498 };
 499 #endif
 500
 501 struct smmu_stream_id dev_stream_id[] = {
 502         { 0x100, 0x01, "ETSEC MAC1" },
 503         { 0x104, 0x02, "ETSEC MAC2" },
 504         { 0x108, 0x03, "ETSEC MAC3" },
 505         { 0x10c, 0x04, "PEX1" },
 506         { 0x110, 0x05, "PEX2" },
 507         { 0x114, 0x06, "qDMA" },
 508         { 0x118, 0x07, "SATA" },
 509         { 0x11c, 0x08, "USB3" },
 510         { 0x120, 0x09, "QE" },
 511         { 0x124, 0x0a, "eSDHC" },
 512         { 0x128, 0x0b, "eMA" },
 513         { 0x14c, 0x0c, "2D-ACE" },
 514         { 0x150, 0x0d, "USB2" },
 515         { 0x18c, 0x0e, "DEBUG" },
 516 };
 517
 518 int board_init(void)
 519 {
 520         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 521
 522         /* Set CCI-400 control override register to
 523          * enable barrier transaction */
 524         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 525
 526         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 527
 528 #ifndef CONFIG_SYS_FSL_NO_SERDES
 529         fsl_serdes_init();
 530         config_serdes_mux();
 531 #endif
 532
 533         ls102xa_config_smmu_stream_id(dev_stream_id,
 534                                       ARRAY_SIZE(dev_stream_id));
 535
 536 #ifdef CONFIG_LS102XA_NS_ACCESS
 537         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 538 #endif
 539
 540 #ifdef CONFIG_U_QE
 541         u_qe_init();
 542 #endif
 543
 544         return 0;
 545 }
 546
 547 int ft_board_setup(void *blob, bd_t *bd)
 548 {
 549         ft_cpu_setup(blob, bd);
 550
 551 #ifdef CONFIG_PCIE_LAYERSCAPE
 552         ft_pcie_setup(blob, bd);
 553 #endif
 554
 555         return 0;
 556 }
 557
 558 u8 flash_read8(void *addr)
 559 {
 560         return __raw_readb(addr + 1);
 561 }
 562
 563 void flash_write16(u16 val, void *addr)
 564 {
 565         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 566
 567         __raw_writew(shftval, addr);
 568 }
 569
 570 u16 flash_read16(void *addr)
 571 {
 572         u16 val = __raw_readw(addr);
 573
 574         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 575 }