]> git.karo-electronics.de Git - karo-tx-uboot.git/blob - board/freescale/ls1021atwr/ls1021atwr.c
arm: ls102xa: Update PCIe dts node status
[karo-tx-uboot.git] / board / freescale / ls1021atwr / ls1021atwr.c
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/pcie_layerscape.h>
14 #include <mmc.h>
15 #include <fsl_esdhc.h>
16 #include <fsl_ifc.h>
17 #include <netdev.h>
18 #include <fsl_mdio.h>
19 #include <tsec.h>
20 #include <fsl_sec.h>
21 #ifdef CONFIG_U_QE
22 #include "../../../drivers/qe/qe.h"
23 #endif
24
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define VERSION_MASK            0x00FF
29 #define BANK_MASK               0x0001
30 #define CONFIG_RESET            0x1
31 #define INIT_RESET              0x1
32
33 #define CPLD_SET_MUX_SERDES     0x20
34 #define CPLD_SET_BOOT_BANK      0x40
35
36 #define BOOT_FROM_UPPER_BANK    0x0
37 #define BOOT_FROM_LOWER_BANK    0x1
38
39 #define LANEB_SATA              (0x01)
40 #define LANEB_SGMII1            (0x02)
41 #define LANEC_SGMII1            (0x04)
42 #define LANEC_PCIEX1            (0x08)
43 #define LANED_PCIEX2            (0x10)
44 #define LANED_SGMII2            (0x20)
45
46 #define MASK_LANE_B             0x1
47 #define MASK_LANE_C             0x2
48 #define MASK_LANE_D             0x4
49 #define MASK_SGMII              0x8
50
51 #define KEEP_STATUS             0x0
52 #define NEED_RESET              0x1
53
54 struct cpld_data {
55         u8 cpld_ver;            /* cpld revision */
56         u8 cpld_ver_sub;        /* cpld sub revision */
57         u8 pcba_ver;            /* pcb revision number */
58         u8 system_rst;          /* reset system by cpld */
59         u8 soft_mux_on;         /* CPLD override physical switches Enable */
60         u8 cfg_rcw_src1;        /* Reset config word 1 */
61         u8 cfg_rcw_src2;        /* Reset config word 2 */
62         u8 vbank;               /* Flash bank selection Control */
63         u8 gpio;                /* GPIO for TWR-ELEV */
64         u8 i2c3_ifc_mux;
65         u8 mux_spi2;
66         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
67         u8 qe_lcd_mux;          /* QE and LCD Selection */
68         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
69         u8 global_rst;          /* reset with init CPLD reg to default */
70         u8 rev1;                /* Reserved */
71         u8 rev2;                /* Reserved */
72 };
73
74 static void convert_serdes_mux(int type, int need_reset);
75
76 void cpld_show(void)
77 {
78         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
79
80         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
81                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
82                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
83                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
84                in_8(&cpld_data->vbank) & BANK_MASK);
85
86 #ifdef CONFIG_DEBUG
87         printf("soft_mux_on =%x\n",
88                in_8(&cpld_data->soft_mux_on));
89         printf("cfg_rcw_src1 =%x\n",
90                in_8(&cpld_data->cfg_rcw_src1));
91         printf("cfg_rcw_src2 =%x\n",
92                in_8(&cpld_data->cfg_rcw_src2));
93         printf("vbank =%x\n",
94                in_8(&cpld_data->vbank));
95         printf("gpio =%x\n",
96                in_8(&cpld_data->gpio));
97         printf("i2c3_ifc_mux =%x\n",
98                in_8(&cpld_data->i2c3_ifc_mux));
99         printf("mux_spi2 =%x\n",
100                in_8(&cpld_data->mux_spi2));
101         printf("can3_usb2_mux =%x\n",
102                in_8(&cpld_data->can3_usb2_mux));
103         printf("qe_lcd_mux =%x\n",
104                in_8(&cpld_data->qe_lcd_mux));
105         printf("serdes_mux =%x\n",
106                in_8(&cpld_data->serdes_mux));
107 #endif
108 }
109
110 int checkboard(void)
111 {
112         puts("Board: LS1021ATWR\n");
113         cpld_show();
114
115         return 0;
116 }
117
118 void ddrmc_init(void)
119 {
120         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
121
122         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
123
124         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
125         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
126
127         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
128         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
129         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
130         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
131         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
132         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
133
134         out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
135
136         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
137         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
138
139         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
140
141         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
142
143         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
144         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
145
146         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
147         out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
148
149         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
150         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
151
152         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
153         udelay(1);
154         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
155 }
156
157 int dram_init(void)
158 {
159 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
160         ddrmc_init();
161 #endif
162
163         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
164         return 0;
165 }
166
167 #ifdef CONFIG_FSL_ESDHC
168 struct fsl_esdhc_cfg esdhc_cfg[1] = {
169         {CONFIG_SYS_FSL_ESDHC_ADDR},
170 };
171
172 int board_mmc_init(bd_t *bis)
173 {
174         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
175
176         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
177 }
178 #endif
179
180 #ifdef CONFIG_TSEC_ENET
181 int board_eth_init(bd_t *bis)
182 {
183         struct fsl_pq_mdio_info mdio_info;
184         struct tsec_info_struct tsec_info[4];
185         int num = 0;
186
187 #ifdef CONFIG_TSEC1
188         SET_STD_TSEC_INFO(tsec_info[num], 1);
189         if (is_serdes_configured(SGMII_TSEC1)) {
190                 puts("eTSEC1 is in sgmii mode.\n");
191                 tsec_info[num].flags |= TSEC_SGMII;
192         }
193         num++;
194 #endif
195 #ifdef CONFIG_TSEC2
196         SET_STD_TSEC_INFO(tsec_info[num], 2);
197         if (is_serdes_configured(SGMII_TSEC2)) {
198                 puts("eTSEC2 is in sgmii mode.\n");
199                 tsec_info[num].flags |= TSEC_SGMII;
200         }
201         num++;
202 #endif
203 #ifdef CONFIG_TSEC3
204         SET_STD_TSEC_INFO(tsec_info[num], 3);
205         num++;
206 #endif
207         if (!num) {
208                 printf("No TSECs initialized\n");
209                 return 0;
210         }
211
212         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
213         mdio_info.name = DEFAULT_MII_NAME;
214         fsl_pq_mdio_init(bis, &mdio_info);
215
216         tsec_eth_init(bis, tsec_info, num);
217
218         return pci_eth_init(bis);
219 }
220 #endif
221
222 int config_serdes_mux(void)
223 {
224         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
225         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
226
227         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
228         switch (protocol) {
229         case 0x10:
230                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
231                 convert_serdes_mux(LANED_PCIEX2 |
232                                 LANEC_PCIEX1, KEEP_STATUS);
233                 break;
234         case 0x20:
235                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
236                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
237                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
238                 break;
239         case 0x30:
240                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
241                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
242                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
243                 break;
244         case 0x70:
245                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
246                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
247                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
248                 break;
249         }
250
251         return 0;
252 }
253
254 int board_early_init_f(void)
255 {
256         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
257
258 #ifdef CONFIG_TSEC_ENET
259         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
260         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
261 #endif
262
263 #ifdef CONFIG_FSL_IFC
264         init_early_memctl_regs();
265 #endif
266
267 #ifdef CONFIG_FSL_DCU_FB
268         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
269 #endif
270
271         return 0;
272 }
273
274 int board_init(void)
275 {
276         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
277
278         /*
279          * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
280          * All transactions are treated as non-shareable
281          */
282         out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
283         out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
284         out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
285
286 #ifndef CONFIG_SYS_FSL_NO_SERDES
287         fsl_serdes_init();
288         config_serdes_mux();
289 #endif
290
291 #ifdef CONFIG_U_QE
292         u_qe_init();
293 #endif
294
295         return 0;
296 }
297
298 #if defined(CONFIG_MISC_INIT_R)
299 int misc_init_r(void)
300 {
301 #ifdef CONFIG_FSL_CAAM
302         return sec_init();
303 #endif
304 }
305 #endif
306
307 int ft_board_setup(void *blob, bd_t *bd)
308 {
309         ft_cpu_setup(blob, bd);
310
311 #ifdef CONFIG_PCIE_LAYERSCAPE
312         ft_pcie_setup(blob, bd);
313 #endif
314
315         return 0;
316 }
317
318 u8 flash_read8(void *addr)
319 {
320         return __raw_readb(addr + 1);
321 }
322
323 void flash_write16(u16 val, void *addr)
324 {
325         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
326
327         __raw_writew(shftval, addr);
328 }
329
330 u16 flash_read16(void *addr)
331 {
332         u16 val = __raw_readw(addr);
333
334         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
335 }
336
337 static void convert_flash_bank(char bank)
338 {
339         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
340
341         printf("Now switch to boot from flash bank %d.\n", bank);
342         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
343         cpld_data->vbank = bank;
344
345         printf("Reset board to enable configuration.\n");
346         cpld_data->system_rst = CONFIG_RESET;
347 }
348
349 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
350                           char * const argv[])
351 {
352         if (argc != 2)
353                 return CMD_RET_USAGE;
354         if (strcmp(argv[1], "0") == 0)
355                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
356         else if (strcmp(argv[1], "1") == 0)
357                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
358         else
359                 return CMD_RET_USAGE;
360
361         return 0;
362 }
363
364 U_BOOT_CMD(
365         boot_bank, 2, 0, flash_bank_cmd,
366         "Flash bank Selection Control",
367         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
368 );
369
370 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
371                           char * const argv[])
372 {
373         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
374
375         if (argc > 2)
376                 return CMD_RET_USAGE;
377         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
378                 cpld_data->system_rst = CONFIG_RESET;
379         else if (strcmp(argv[1], "init") == 0)
380                 cpld_data->global_rst = INIT_RESET;
381         else
382                 return CMD_RET_USAGE;
383
384         return 0;
385 }
386
387 U_BOOT_CMD(
388         cpld_reset, 2, 0, cpld_reset_cmd,
389         "Reset via CPLD",
390         "conf\n"
391         "       -reset with current CPLD configuration\n"
392         "init\n"
393         "       -reset and initial CPLD configuration with default value"
394
395 );
396
397 static void convert_serdes_mux(int type, int need_reset)
398 {
399         char current_serdes;
400         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
401
402         current_serdes = cpld_data->serdes_mux;
403
404         switch (type) {
405         case LANEB_SATA:
406                 current_serdes &= ~MASK_LANE_B;
407                 break;
408         case LANEB_SGMII1:
409                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
410                 break;
411         case LANEC_SGMII1:
412                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
413                 break;
414         case LANED_SGMII2:
415                 current_serdes |= MASK_LANE_D;
416                 break;
417         case LANEC_PCIEX1:
418                 current_serdes |= MASK_LANE_C;
419                 break;
420         case (LANED_PCIEX2 | LANEC_PCIEX1):
421                 current_serdes |= MASK_LANE_C;
422                 current_serdes &= ~MASK_LANE_D;
423                 break;
424         default:
425                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
426                 return;
427         }
428
429         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
430         cpld_data->serdes_mux = current_serdes;
431
432         if (need_reset == 1) {
433                 printf("Reset board to enable configuration\n");
434                 cpld_data->system_rst = CONFIG_RESET;
435         }
436 }
437
438 void print_serdes_mux(void)
439 {
440         char current_serdes;
441         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
442
443         current_serdes = cpld_data->serdes_mux;
444
445         printf("Serdes Lane B: ");
446         if ((current_serdes & MASK_LANE_B) == 0)
447                 printf("SATA,\n");
448         else
449                 printf("SGMII 1,\n");
450
451         printf("Serdes Lane C: ");
452         if ((current_serdes & MASK_LANE_C) == 0)
453                 printf("SGMII 1,\n");
454         else
455                 printf("PCIe,\n");
456
457         printf("Serdes Lane D: ");
458         if ((current_serdes & MASK_LANE_D) == 0)
459                 printf("PCIe,\n");
460         else
461                 printf("SGMII 2,\n");
462
463         printf("SGMII 1 is on lane ");
464         if ((current_serdes & MASK_SGMII) == 0)
465                 printf("C.\n");
466         else
467                 printf("B.\n");
468 }
469
470 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
471                           char * const argv[])
472 {
473         if (argc != 2)
474                 return CMD_RET_USAGE;
475         if (strcmp(argv[1], "sata") == 0) {
476                 printf("Set serdes lane B to SATA.\n");
477                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
478         } else if (strcmp(argv[1], "sgmii1b") == 0) {
479                 printf("Set serdes lane B to SGMII 1.\n");
480                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
481         } else if (strcmp(argv[1], "sgmii1c") == 0) {
482                 printf("Set serdes lane C to SGMII 1.\n");
483                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
484         } else if (strcmp(argv[1], "sgmii2") == 0) {
485                 printf("Set serdes lane D to SGMII 2.\n");
486                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
487         } else if (strcmp(argv[1], "pciex1") == 0) {
488                 printf("Set serdes lane C to PCIe X1.\n");
489                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
490         } else if (strcmp(argv[1], "pciex2") == 0) {
491                 printf("Set serdes lane C & lane D to PCIe X2.\n");
492                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
493         } else if (strcmp(argv[1], "show") == 0) {
494                 print_serdes_mux();
495         } else {
496                 return CMD_RET_USAGE;
497         }
498
499         return 0;
500 }
501
502 U_BOOT_CMD(
503         lane_bank, 2, 0, serdes_mux_cmd,
504         "Multiplexed function setting for SerDes Lanes",
505         "sata\n"
506         "       -change lane B to sata\n"
507         "lane_bank sgmii1b\n"
508         "       -change lane B to SGMII1\n"
509         "lane_bank sgmii1c\n"
510         "       -change lane C to SGMII1\n"
511         "lane_bank sgmii2\n"
512         "       -change lane D to SGMII2\n"
513         "lane_bank pciex1\n"
514         "       -change lane C to PCIeX1\n"
515         "lane_bank pciex2\n"
516         "       -change lane C & lane D to PCIeX2\n"
517         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
518 );