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[karo-tx-uboot.git] / board / freescale / ls1021atwr / ls1021atwr.c
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <fsl_ifc.h>
16 #include <netdev.h>
17 #include <fsl_mdio.h>
18 #include <tsec.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #define VERSION_MASK            0x00FF
23 #define BANK_MASK               0x0001
24 #define CONFIG_RESET            0x1
25 #define INIT_RESET              0x1
26
27 #define CPLD_SET_MUX_SERDES     0x20
28 #define CPLD_SET_BOOT_BANK      0x40
29
30 #define BOOT_FROM_UPPER_BANK    0x0
31 #define BOOT_FROM_LOWER_BANK    0x1
32
33 #define LANEB_SATA              (0x01)
34 #define LANEB_SGMII1            (0x02)
35 #define LANEC_SGMII1            (0x04)
36 #define LANEC_PCIEX1            (0x08)
37 #define LANED_PCIEX2            (0x10)
38 #define LANED_SGMII2            (0x20)
39
40 #define MASK_LANE_B             0x1
41 #define MASK_LANE_C             0x2
42 #define MASK_LANE_D             0x4
43 #define MASK_SGMII              0x8
44
45 #define KEEP_STATUS             0x0
46 #define NEED_RESET              0x1
47
48 struct cpld_data {
49         u8 cpld_ver;            /* cpld revision */
50         u8 cpld_ver_sub;        /* cpld sub revision */
51         u8 pcba_ver;            /* pcb revision number */
52         u8 system_rst;          /* reset system by cpld */
53         u8 soft_mux_on;         /* CPLD override physical switches Enable */
54         u8 cfg_rcw_src1;        /* Reset config word 1 */
55         u8 cfg_rcw_src2;        /* Reset config word 2 */
56         u8 vbank;               /* Flash bank selection Control */
57         u8 gpio;                /* GPIO for TWR-ELEV */
58         u8 i2c3_ifc_mux;
59         u8 mux_spi2;
60         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
61         u8 qe_lcd_mux;          /* QE and LCD Selection */
62         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
63         u8 global_rst;          /* reset with init CPLD reg to default */
64         u8 rev1;                /* Reserved */
65         u8 rev2;                /* Reserved */
66 };
67
68 static void convert_serdes_mux(int type, int need_reset);
69
70 void cpld_show(void)
71 {
72         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
73
74         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
75                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
76                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
77                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
78                in_8(&cpld_data->vbank) & BANK_MASK);
79
80 #ifdef CONFIG_DEBUG
81         printf("soft_mux_on =%x\n",
82                in_8(&cpld_data->soft_mux_on));
83         printf("cfg_rcw_src1 =%x\n",
84                in_8(&cpld_data->cfg_rcw_src1));
85         printf("cfg_rcw_src2 =%x\n",
86                in_8(&cpld_data->cfg_rcw_src2));
87         printf("vbank =%x\n",
88                in_8(&cpld_data->vbank));
89         printf("gpio =%x\n",
90                in_8(&cpld_data->gpio));
91         printf("i2c3_ifc_mux =%x\n",
92                in_8(&cpld_data->i2c3_ifc_mux));
93         printf("mux_spi2 =%x\n",
94                in_8(&cpld_data->mux_spi2));
95         printf("can3_usb2_mux =%x\n",
96                in_8(&cpld_data->can3_usb2_mux));
97         printf("qe_lcd_mux =%x\n",
98                in_8(&cpld_data->qe_lcd_mux));
99         printf("serdes_mux =%x\n",
100                in_8(&cpld_data->serdes_mux));
101 #endif
102 }
103
104 int checkboard(void)
105 {
106         puts("Board: LS1021ATWR\n");
107         cpld_show();
108
109         return 0;
110 }
111
112 void ddrmc_init(void)
113 {
114         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
115
116         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
117
118         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
119         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
120
121         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
122         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
123         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
124         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
125         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
126         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
127
128         out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
129
130         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
131         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
132
133         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
134
135         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
136
137         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
138         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
139
140         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
141         out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
142
143         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
144         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
145
146         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
147         udelay(1);
148         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
149 }
150
151 int dram_init(void)
152 {
153 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
154         ddrmc_init();
155 #endif
156
157         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
158         return 0;
159 }
160
161 #ifdef CONFIG_FSL_ESDHC
162 struct fsl_esdhc_cfg esdhc_cfg[1] = {
163         {CONFIG_SYS_FSL_ESDHC_ADDR},
164 };
165
166 int board_mmc_init(bd_t *bis)
167 {
168         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
169
170         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
171 }
172 #endif
173
174 #ifdef CONFIG_TSEC_ENET
175 int board_eth_init(bd_t *bis)
176 {
177         struct fsl_pq_mdio_info mdio_info;
178         struct tsec_info_struct tsec_info[4];
179         int num = 0;
180
181 #ifdef CONFIG_TSEC1
182         SET_STD_TSEC_INFO(tsec_info[num], 1);
183         if (is_serdes_configured(SGMII_TSEC1)) {
184                 puts("eTSEC1 is in sgmii mode.\n");
185                 tsec_info[num].flags |= TSEC_SGMII;
186         }
187         num++;
188 #endif
189 #ifdef CONFIG_TSEC2
190         SET_STD_TSEC_INFO(tsec_info[num], 2);
191         if (is_serdes_configured(SGMII_TSEC2)) {
192                 puts("eTSEC2 is in sgmii mode.\n");
193                 tsec_info[num].flags |= TSEC_SGMII;
194         }
195         num++;
196 #endif
197 #ifdef CONFIG_TSEC3
198         SET_STD_TSEC_INFO(tsec_info[num], 3);
199         num++;
200 #endif
201         if (!num) {
202                 printf("No TSECs initialized\n");
203                 return 0;
204         }
205
206         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
207         mdio_info.name = DEFAULT_MII_NAME;
208         fsl_pq_mdio_init(bis, &mdio_info);
209
210         tsec_eth_init(bis, tsec_info, num);
211
212         return pci_eth_init(bis);
213 }
214 #endif
215
216 int config_serdes_mux(void)
217 {
218         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
219         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
220
221         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
222         switch (protocol) {
223         case 0x10:
224                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
225                 convert_serdes_mux(LANED_PCIEX2 |
226                                 LANEC_PCIEX1, KEEP_STATUS);
227                 break;
228         case 0x20:
229                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
230                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
231                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
232                 break;
233         case 0x30:
234                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
235                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
236                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
237                 break;
238         case 0x70:
239                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
240                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
241                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
242                 break;
243         }
244
245         return 0;
246 }
247
248 int board_early_init_f(void)
249 {
250         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
251
252 #ifdef CONFIG_TSEC_ENET
253         out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
254         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
255         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
256         udelay(10);
257         out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
258 #endif
259
260 #ifdef CONFIG_FSL_IFC
261         init_early_memctl_regs();
262 #endif
263
264 #ifdef CONFIG_FSL_DCU_FB
265         out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
266         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
267         out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
268 #endif
269
270         return 0;
271 }
272
273 int board_init(void)
274 {
275 #ifndef CONFIG_SYS_FSL_NO_SERDES
276         fsl_serdes_init();
277         config_serdes_mux();
278 #endif
279
280         return 0;
281 }
282
283 void ft_board_setup(void *blob, bd_t *bd)
284 {
285         ft_cpu_setup(blob, bd);
286 }
287
288 u8 flash_read8(void *addr)
289 {
290         return __raw_readb(addr + 1);
291 }
292
293 void flash_write16(u16 val, void *addr)
294 {
295         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
296
297         __raw_writew(shftval, addr);
298 }
299
300 u16 flash_read16(void *addr)
301 {
302         u16 val = __raw_readw(addr);
303
304         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
305 }
306
307 static void convert_flash_bank(char bank)
308 {
309         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
310
311         printf("Now switch to boot from flash bank %d.\n", bank);
312         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
313         cpld_data->vbank = bank;
314
315         printf("Reset board to enable configuration.\n");
316         cpld_data->system_rst = CONFIG_RESET;
317 }
318
319 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
320                           char * const argv[])
321 {
322         if (argc != 2)
323                 return CMD_RET_USAGE;
324         if (strcmp(argv[1], "0") == 0)
325                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
326         else if (strcmp(argv[1], "1") == 0)
327                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
328         else
329                 return CMD_RET_USAGE;
330
331         return 0;
332 }
333
334 U_BOOT_CMD(
335         boot_bank, 2, 0, flash_bank_cmd,
336         "Flash bank Selection Control",
337         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
338 );
339
340 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
341                           char * const argv[])
342 {
343         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
344
345         if (argc > 2)
346                 return CMD_RET_USAGE;
347         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
348                 cpld_data->system_rst = CONFIG_RESET;
349         else if (strcmp(argv[1], "init") == 0)
350                 cpld_data->global_rst = INIT_RESET;
351         else
352                 return CMD_RET_USAGE;
353
354         return 0;
355 }
356
357 U_BOOT_CMD(
358         cpld_reset, 2, 0, cpld_reset_cmd,
359         "Reset via CPLD",
360         "conf\n"
361         "       -reset with current CPLD configuration\n"
362         "init\n"
363         "       -reset and initial CPLD configuration with default value"
364
365 );
366
367 static void convert_serdes_mux(int type, int need_reset)
368 {
369         char current_serdes;
370         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
371
372         current_serdes = cpld_data->serdes_mux;
373
374         switch (type) {
375         case LANEB_SATA:
376                 current_serdes &= ~MASK_LANE_B;
377                 break;
378         case LANEB_SGMII1:
379                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
380                 break;
381         case LANEC_SGMII1:
382                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
383                 break;
384         case LANED_SGMII2:
385                 current_serdes |= MASK_LANE_D;
386                 break;
387         case LANEC_PCIEX1:
388                 current_serdes |= MASK_LANE_C;
389                 break;
390         case (LANED_PCIEX2 | LANEC_PCIEX1):
391                 current_serdes |= MASK_LANE_C;
392                 current_serdes &= ~MASK_LANE_D;
393                 break;
394         default:
395                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
396                 return;
397         }
398
399         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
400         cpld_data->serdes_mux = current_serdes;
401
402         if (need_reset == 1) {
403                 printf("Reset board to enable configuration\n");
404                 cpld_data->system_rst = CONFIG_RESET;
405         }
406 }
407
408 void print_serdes_mux(void)
409 {
410         char current_serdes;
411         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
412
413         current_serdes = cpld_data->serdes_mux;
414
415         printf("Serdes Lane B: ");
416         if ((current_serdes & MASK_LANE_B) == 0)
417                 printf("SATA,\n");
418         else
419                 printf("SGMII 1,\n");
420
421         printf("Serdes Lane C: ");
422         if ((current_serdes & MASK_LANE_C) == 0)
423                 printf("SGMII 1,\n");
424         else
425                 printf("PCIe,\n");
426
427         printf("Serdes Lane D: ");
428         if ((current_serdes & MASK_LANE_D) == 0)
429                 printf("PCIe,\n");
430         else
431                 printf("SGMII 2,\n");
432
433         printf("SGMII 1 is on lane ");
434         if ((current_serdes & MASK_SGMII) == 0)
435                 printf("C.\n");
436         else
437                 printf("B.\n");
438 }
439
440 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
441                           char * const argv[])
442 {
443         if (argc != 2)
444                 return CMD_RET_USAGE;
445         if (strcmp(argv[1], "sata") == 0) {
446                 printf("Set serdes lane B to SATA.\n");
447                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
448         } else if (strcmp(argv[1], "sgmii1b") == 0) {
449                 printf("Set serdes lane B to SGMII 1.\n");
450                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
451         } else if (strcmp(argv[1], "sgmii1c") == 0) {
452                 printf("Set serdes lane C to SGMII 1.\n");
453                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
454         } else if (strcmp(argv[1], "sgmii2") == 0) {
455                 printf("Set serdes lane D to SGMII 2.\n");
456                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
457         } else if (strcmp(argv[1], "pciex1") == 0) {
458                 printf("Set serdes lane C to PCIe X1.\n");
459                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
460         } else if (strcmp(argv[1], "pciex2") == 0) {
461                 printf("Set serdes lane C & lane D to PCIe X2.\n");
462                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
463         } else if (strcmp(argv[1], "show") == 0) {
464                 print_serdes_mux();
465         } else {
466                 return CMD_RET_USAGE;
467         }
468
469         return 0;
470 }
471
472 U_BOOT_CMD(
473         lane_bank, 2, 0, serdes_mux_cmd,
474         "Multiplexed function setting for SerDes Lanes",
475         "sata\n"
476         "       -change lane B to sata\n"
477         "lane_bank sgmii1b\n"
478         "       -change lane B to SGMII1\n"
479         "lane_bank sgmii1c\n"
480         "       -change lane C to SGMII1\n"
481         "lane_bank sgmii2\n"
482         "       -change lane D to SGMII2\n"
483         "lane_bank pciex1\n"
484         "       -change lane C to PCIeX1\n"
485         "lane_bank pciex2\n"
486         "       -change lane C & lane D to PCIeX2\n"
487         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
488 );