2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
15 #include <fsl_debug_server.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
19 #include <asm/arch-fsl-lsch3/soc.h>
21 #include "../common/qixis.h"
22 #include "ls2085aqds_qixis.h"
24 DECLARE_GLOBAL_DATA_PTR;
26 unsigned long long get_qixis_addr(void)
28 unsigned long long addr;
30 if (gd->flags & GD_FLG_RELOC)
31 addr = QIXIS_BASE_PHYS;
33 addr = QIXIS_BASE_PHYS_EARLY;
36 * IFC address under 256MB is mapped to 0x30000000, any address above
37 * is mapped to 0x5_10000000 up to 4GB.
39 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
48 static const char *const freq[] = {"100", "125", "156.25",
52 sw = QIXIS_READ(arch);
53 printf("Board: %s, ", CONFIG_IDENT_STRING);
54 printf("Board Arch: V%d, ", sw >> 4);
55 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
57 sw = QIXIS_READ(brdcfg[0]);
58 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
61 printf("vBank: %d\n", sw);
69 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
71 printf("FPGA: v%d (%s), build %d",
72 (int)QIXIS_READ(scver), qixis_read_tag(buf),
73 (int)qixis_read_minor());
74 /* the timestamp string contains "\n" at the end */
75 printf(" on %s", qixis_read_time(buf));
78 * Display the actual SERDES reference clocks as configured by the
79 * dip switches on the board. Note that the SWx registers could
80 * technically be set to force the reference clocks to match the
81 * values that the SERDES expects (or vice versa). For now, however,
82 * we just display both values and hope the user notices when they
85 puts("SERDES1 Reference : ");
86 sw = QIXIS_READ(brdcfg[2]);
87 clock = (sw >> 6) & 3;
88 printf("Clock1 = %sMHz ", freq[clock]);
89 clock = (sw >> 4) & 3;
90 printf("Clock2 = %sMHz", freq[clock]);
92 puts("\nSERDES2 Reference : ");
93 clock = (sw >> 2) & 3;
94 printf("Clock1 = %sMHz ", freq[clock]);
95 clock = (sw >> 0) & 3;
96 printf("Clock2 = %sMHz\n", freq[clock]);
101 unsigned long get_board_sys_clk(void)
103 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
105 switch (sysclk_conf & 0x0F) {
106 case QIXIS_SYSCLK_83:
108 case QIXIS_SYSCLK_100:
110 case QIXIS_SYSCLK_125:
112 case QIXIS_SYSCLK_133:
114 case QIXIS_SYSCLK_150:
116 case QIXIS_SYSCLK_160:
118 case QIXIS_SYSCLK_166:
124 unsigned long get_board_ddr_clk(void)
126 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
128 switch ((ddrclk_conf & 0x30) >> 4) {
129 case QIXIS_DDRCLK_100:
131 case QIXIS_DDRCLK_125:
133 case QIXIS_DDRCLK_133:
139 int select_i2c_ch_pca9547(u8 ch)
143 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
145 puts("PCA: failed to select proper channel\n");
154 init_final_memctl_regs();
156 #ifdef CONFIG_ENV_IS_NOWHERE
157 gd->env_addr = (ulong)&default_environment[0];
159 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
164 int board_early_init_f(void)
166 fsl_lsch3_early_init_f();
170 void detail_board_ddr_info(void)
173 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
175 if (gd->bd->bi_dram[2].size) {
177 print_size(gd->bd->bi_dram[2].size, "");
178 print_ddr_info(CONFIG_DP_DDR_CTRL);
184 gd->ram_size = initdram(0);
189 #if defined(CONFIG_ARCH_MISC_INIT)
190 int arch_misc_init(void)
192 #ifdef CONFIG_FSL_DEBUG_SERVER
200 unsigned long get_dram_size_to_hide(void)
202 unsigned long dram_to_hide = 0;
204 /* Carve the Debug Server private DRAM block from the end of DRAM */
205 #ifdef CONFIG_FSL_DEBUG_SERVER
206 dram_to_hide += debug_server_get_dram_block_size();
209 /* Carve the MC private DRAM block from the end of DRAM */
210 #ifdef CONFIG_FSL_MC_ENET
211 dram_to_hide += mc_get_dram_block_size();
217 int board_eth_init(bd_t *bis)
221 #ifdef CONFIG_FSL_MC_ENET
222 error = cpu_eth_init(bis);
225 error = pci_eth_init(bis);
230 #ifdef CONFIG_FSL_MC_ENET
231 void fdt_fixup_board_enet(void *fdt)
235 offset = fdt_path_offset(fdt, "/fsl-mc");
238 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
241 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
246 if (get_mc_boot_status() == 0)
247 fdt_status_okay(fdt, offset);
249 fdt_status_fail(fdt, offset);
253 #ifdef CONFIG_OF_BOARD_SETUP
254 int ft_board_setup(void *blob, bd_t *bd)
259 ft_cpu_setup(blob, bd);
261 /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
262 base = getenv_bootm_low();
263 size = getenv_bootm_size();
264 fdt_fixup_memory(blob, (u64)base, (u64)size);
266 #ifdef CONFIG_FSL_MC_ENET
267 fdt_fixup_board_enet(blob);
268 fsl_mc_ldpaa_exit(bd);
275 void qixis_dump_switch(void)
279 QIXIS_WRITE(cms[0], 0x00);
280 nr_of_cfgsw = QIXIS_READ(cms[1]);
282 puts("DIP switch settings dump:\n");
283 for (i = 1; i <= nr_of_cfgsw; i++) {
284 QIXIS_WRITE(cms[0], i);
285 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));