2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
15 #include <fsl_debug_server.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
19 #include <asm/arch-fsl-lsch3/soc.h>
21 #include "../common/qixis.h"
22 #include "ls2085ardb_qixis.h"
24 DECLARE_GLOBAL_DATA_PTR;
26 unsigned long long get_qixis_addr(void)
28 unsigned long long addr;
30 if (gd->flags & GD_FLG_RELOC)
31 addr = QIXIS_BASE_PHYS;
33 addr = QIXIS_BASE_PHYS_EARLY;
36 * IFC address under 256MB is mapped to 0x30000000, any address above
37 * is mapped to 0x5_10000000 up to 4GB.
39 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
48 sw = QIXIS_READ(arch);
49 printf("Board: %s, ", CONFIG_IDENT_STRING);
50 printf("Board Arch: V%d, ", sw >> 4);
51 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
53 sw = QIXIS_READ(brdcfg[0]);
54 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
57 printf("vBank: %d\n", sw);
61 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
63 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
65 puts("SERDES1 Reference : ");
66 printf("Clock1 = 156.25MHz ");
67 printf("Clock2 = 156.25MHz");
69 puts("\nSERDES2 Reference : ");
70 printf("Clock1 = 100MHz ");
71 printf("Clock2 = 100MHz\n");
76 unsigned long get_board_sys_clk(void)
78 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
80 switch (sysclk_conf & 0x0F) {
83 case QIXIS_SYSCLK_100:
85 case QIXIS_SYSCLK_125:
87 case QIXIS_SYSCLK_133:
89 case QIXIS_SYSCLK_150:
91 case QIXIS_SYSCLK_160:
93 case QIXIS_SYSCLK_166:
99 int select_i2c_ch_pca9547(u8 ch)
103 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
105 puts("PCA: failed to select proper channel\n");
114 init_final_memctl_regs();
116 #ifdef CONFIG_ENV_IS_NOWHERE
117 gd->env_addr = (ulong)&default_environment[0];
119 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
121 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
126 int board_early_init_f(void)
128 fsl_lsch3_early_init_f();
132 void detail_board_ddr_info(void)
135 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
137 if (gd->bd->bi_dram[2].size) {
139 print_size(gd->bd->bi_dram[2].size, "");
140 print_ddr_info(CONFIG_DP_DDR_CTRL);
146 gd->ram_size = initdram(0);
151 #if defined(CONFIG_ARCH_MISC_INIT)
152 int arch_misc_init(void)
154 #ifdef CONFIG_FSL_DEBUG_SERVER
162 unsigned long get_dram_size_to_hide(void)
164 unsigned long dram_to_hide = 0;
166 /* Carve the Debug Server private DRAM block from the end of DRAM */
167 #ifdef CONFIG_FSL_DEBUG_SERVER
168 dram_to_hide += debug_server_get_dram_block_size();
171 /* Carve the MC private DRAM block from the end of DRAM */
172 #ifdef CONFIG_FSL_MC_ENET
173 dram_to_hide += mc_get_dram_block_size();
179 int board_eth_init(bd_t *bis)
183 #ifdef CONFIG_FSL_MC_ENET
184 error = cpu_eth_init(bis);
187 error = pci_eth_init(bis);
192 #ifdef CONFIG_FSL_MC_ENET
193 void fdt_fixup_board_enet(void *fdt)
197 offset = fdt_path_offset(fdt, "/fsl-mc");
200 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
203 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
208 if (get_mc_boot_status() == 0)
209 fdt_status_okay(fdt, offset);
211 fdt_status_fail(fdt, offset);
215 #ifdef CONFIG_OF_BOARD_SETUP
216 int ft_board_setup(void *blob, bd_t *bd)
221 ft_cpu_setup(blob, bd);
223 /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
224 base = getenv_bootm_low();
225 size = getenv_bootm_size();
226 fdt_fixup_memory(blob, (u64)base, (u64)size);
228 #ifdef CONFIG_FSL_MC_ENET
229 fdt_fixup_board_enet(blob);
230 fsl_mc_ldpaa_exit(bd);
237 void qixis_dump_switch(void)
241 QIXIS_WRITE(cms[0], 0x00);
242 nr_of_cfgsw = QIXIS_READ(cms[1]);
244 puts("DIP switch settings dump:\n");
245 for (i = 1; i <= nr_of_cfgsw; i++) {
246 QIXIS_WRITE(cms[0], i);
247 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));