2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
37 #include "../common/pixis.h"
38 #include "../common/sgmii_riser.h"
40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
41 extern void ddr_enable_ecc(unsigned int dram_size);
46 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
47 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
48 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
50 if ((uint)&gur->porpllsr != 0xe00e0000) {
51 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
53 printf ("Board: MPC8544DS, System ID: 0x%02x, "
54 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
55 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
56 in8(PIXIS_BASE + PIXIS_PVER));
58 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
59 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
60 ecm->eedr = 0xffffffff; /* Clear ecm errors */
61 ecm->eeer = 0xffffffff; /* Enable ecm errors */
67 initdram(int board_type)
71 puts("Initializing\n");
73 dram_size = fsl_ddr_sdram();
75 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
77 dram_size *= 0x100000;
79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
81 * Initialize and enable DDR ECC.
83 ddr_enable_ecc(dram_size);
90 static struct pci_controller pci1_hose;
94 static struct pci_controller pcie1_hose;
98 static struct pci_controller pcie2_hose;
102 static struct pci_controller pcie3_hose;
105 int first_free_busno=0;
110 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
111 uint devdisr = gur->devdisr;
112 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
113 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
115 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
116 devdisr, io_sel, host_agent);
119 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
120 printf (" eTSEC1 is in sgmii mode.\n");
121 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
122 printf (" eTSEC3 is in sgmii mode.\n");
127 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
128 extern void fsl_pci_init(struct pci_controller *hose);
129 struct pci_controller *hose = &pcie3_hose;
130 int pcie_ep = (host_agent == 1);
131 int pcie_configured = io_sel >= 1;
133 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
134 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
135 pcie_ep ? "End Point" : "Root Complex",
137 if (pci->pme_msg_det) {
138 pci->pme_msg_det = 0xffffffff;
139 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
144 pci_set_region(hose->regions + 0,
148 PCI_REGION_MEM | PCI_REGION_MEMORY);
150 /* outbound memory */
151 pci_set_region(hose->regions + 1,
158 pci_set_region(hose->regions + 2,
164 hose->region_count = 3;
165 #ifdef CFG_PCIE3_MEM_BASE2
166 /* outbound memory */
167 pci_set_region(hose->regions + 3,
172 hose->region_count++;
174 hose->first_busno=first_free_busno;
175 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
179 first_free_busno=hose->last_busno+1;
180 printf (" PCIE3 on bus %02x - %02x\n",
181 hose->first_busno,hose->last_busno);
184 * Activate ULI1575 legacy chip by performing a fake
185 * memory access. Needed to make ULI RTC work.
187 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
189 printf (" PCIE3: disabled\n");
194 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
199 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
200 extern void fsl_pci_init(struct pci_controller *hose);
201 struct pci_controller *hose = &pcie1_hose;
202 int pcie_ep = (host_agent == 5);
203 int pcie_configured = io_sel & 6;
205 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
206 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
207 pcie_ep ? "End Point" : "Root Complex",
209 if (pci->pme_msg_det) {
210 pci->pme_msg_det = 0xffffffff;
211 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
216 pci_set_region(hose->regions + 0,
220 PCI_REGION_MEM | PCI_REGION_MEMORY);
222 /* outbound memory */
223 pci_set_region(hose->regions + 1,
230 pci_set_region(hose->regions + 2,
236 hose->region_count = 3;
237 #ifdef CFG_PCIE1_MEM_BASE2
238 /* outbound memory */
239 pci_set_region(hose->regions + 3,
244 hose->region_count++;
246 hose->first_busno=first_free_busno;
248 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
252 first_free_busno=hose->last_busno+1;
253 printf(" PCIE1 on bus %02x - %02x\n",
254 hose->first_busno,hose->last_busno);
257 printf (" PCIE1: disabled\n");
262 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
267 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
268 extern void fsl_pci_init(struct pci_controller *hose);
269 struct pci_controller *hose = &pcie2_hose;
270 int pcie_ep = (host_agent == 3);
271 int pcie_configured = io_sel & 4;
273 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
274 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
275 pcie_ep ? "End Point" : "Root Complex",
277 if (pci->pme_msg_det) {
278 pci->pme_msg_det = 0xffffffff;
279 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
284 pci_set_region(hose->regions + 0,
288 PCI_REGION_MEM | PCI_REGION_MEMORY);
290 /* outbound memory */
291 pci_set_region(hose->regions + 1,
298 pci_set_region(hose->regions + 2,
304 hose->region_count = 3;
305 #ifdef CFG_PCIE2_MEM_BASE2
306 /* outbound memory */
307 pci_set_region(hose->regions + 3,
312 hose->region_count++;
314 hose->first_busno=first_free_busno;
315 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
318 first_free_busno=hose->last_busno+1;
319 printf (" PCIE2 on bus %02x - %02x\n",
320 hose->first_busno,hose->last_busno);
323 printf (" PCIE2: disabled\n");
328 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
334 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
335 extern void fsl_pci_init(struct pci_controller *hose);
336 struct pci_controller *hose = &pci1_hose;
338 uint pci_agent = (host_agent == 6);
339 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
341 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
342 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
345 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
346 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
348 (pci_speed == 33333000) ? "33" :
349 (pci_speed == 66666000) ? "66" : "unknown",
350 pci_clk_sel ? "sync" : "async",
351 pci_agent ? "agent" : "host",
352 pci_arb ? "arbiter" : "external-arbiter",
357 pci_set_region(hose->regions + 0,
361 PCI_REGION_MEM | PCI_REGION_MEMORY);
363 /* outbound memory */
364 pci_set_region(hose->regions + 1,
371 pci_set_region(hose->regions + 2,
376 hose->region_count = 3;
377 #ifdef CFG_PCIE3_MEM_BASE2
378 /* outbound memory */
379 pci_set_region(hose->regions + 3,
384 hose->region_count++;
386 hose->first_busno=first_free_busno;
387 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
390 first_free_busno=hose->last_busno+1;
391 printf ("PCI on bus %02x - %02x\n",
392 hose->first_busno,hose->last_busno);
394 printf (" PCI: disabled\n");
398 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
403 int last_stage_init(void)
410 get_board_sys_clk(ulong dummy)
412 u8 i, go_bit, rd_clks;
415 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
418 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
422 * Only if both go bit and the SCLK bit in VCFGEN0 are set
423 * should we be using the AUX register. Remember, we also set the
424 * GO bit to boot from the alternate bank on the on-board flash
429 i = in8(PIXIS_BASE + PIXIS_AUX);
431 i = in8(PIXIS_BASE + PIXIS_SPD);
433 i = in8(PIXIS_BASE + PIXIS_SPD);
468 #ifdef CONFIG_TSEC_ENET
469 int board_eth_init(bd_t *bis)
471 struct tsec_info_struct tsec_info[2];
472 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
473 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
477 SET_STD_TSEC_INFO(tsec_info[num], 1);
478 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
479 tsec_info[num].flags |= TSEC_SGMII;
483 SET_STD_TSEC_INFO(tsec_info[num], 3);
484 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
485 tsec_info[num].flags |= TSEC_SGMII;
490 printf("No TSECs initialized\n");
496 fsl_sgmii_riser_init(tsec_info, num);
499 tsec_eth_init(bis, tsec_info, num);
505 #if defined(CONFIG_OF_BOARD_SETUP)
508 ft_board_setup(void *blob, bd_t *bd)
513 ft_cpu_setup(blob, bd);
515 node = fdt_path_offset(blob, "/aliases");
519 path = fdt_getprop(blob, node, "pci0", NULL);
521 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
522 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
526 path = fdt_getprop(blob, node, "pci1", NULL);
528 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
529 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
533 path = fdt_getprop(blob, node, "pci2", NULL);
535 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
536 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
540 path = fdt_getprop(blob, node, "pci3", NULL);
542 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
543 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);