2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
47 u8 *pixis_base = (u8 *)PIXIS_BASE;
49 if ((uint)&gur->porpllsr != 0xe00e0000) {
50 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
55 in_8(pixis_base + PIXIS_PVER));
57 vboot = in_8(pixis_base + PIXIS_VBOOT);
58 if (vboot & PIXIS_VBOOT_FMAP)
59 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
63 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
64 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
65 ecm->eedr = 0xffffffff; /* Clear ecm errors */
66 ecm->eeer = 0xffffffff; /* Enable ecm errors */
72 initdram(int board_type)
76 puts("Initializing\n");
78 dram_size = fsl_ddr_sdram();
80 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
82 dram_size *= 0x100000;
89 static struct pci_controller pci1_hose;
93 static struct pci_controller pcie1_hose;
97 static struct pci_controller pcie2_hose;
101 static struct pci_controller pcie3_hose;
104 int first_free_busno=0;
109 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
110 uint devdisr = gur->devdisr;
111 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
112 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
114 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
115 devdisr, io_sel, host_agent);
118 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
119 printf (" eTSEC1 is in sgmii mode.\n");
120 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
121 printf (" eTSEC3 is in sgmii mode.\n");
126 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
127 struct pci_controller *hose = &pcie3_hose;
128 int pcie_ep = (host_agent == 1);
129 int pcie_configured = io_sel >= 6;
130 struct pci_region *r = hose->regions;
132 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
133 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
134 pcie_ep ? "End Point" : "Root Complex",
136 if (pci->pme_msg_det) {
137 pci->pme_msg_det = 0xffffffff;
138 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
143 r += fsl_pci_setup_inbound_windows(r);
145 /* outbound memory */
147 CONFIG_SYS_PCIE3_MEM_BUS,
148 CONFIG_SYS_PCIE3_MEM_PHYS,
149 CONFIG_SYS_PCIE3_MEM_SIZE,
154 CONFIG_SYS_PCIE3_IO_BUS,
155 CONFIG_SYS_PCIE3_IO_PHYS,
156 CONFIG_SYS_PCIE3_IO_SIZE,
159 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
160 /* outbound memory */
162 CONFIG_SYS_PCIE3_MEM_BUS2,
163 CONFIG_SYS_PCIE3_MEM_PHYS2,
164 CONFIG_SYS_PCIE3_MEM_SIZE2,
167 hose->region_count = r - hose->regions;
168 hose->first_busno=first_free_busno;
169 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
173 first_free_busno=hose->last_busno+1;
174 printf (" PCIE3 on bus %02x - %02x\n",
175 hose->first_busno,hose->last_busno);
178 * Activate ULI1575 legacy chip by performing a fake
179 * memory access. Needed to make ULI RTC work.
181 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
183 printf (" PCIE3: disabled\n");
188 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
193 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
194 struct pci_controller *hose = &pcie1_hose;
195 int pcie_ep = (host_agent == 5);
196 int pcie_configured = io_sel >= 2;
197 struct pci_region *r = hose->regions;
199 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
200 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
201 pcie_ep ? "End Point" : "Root Complex",
203 if (pci->pme_msg_det) {
204 pci->pme_msg_det = 0xffffffff;
205 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
210 r += fsl_pci_setup_inbound_windows(r);
212 /* outbound memory */
214 CONFIG_SYS_PCIE1_MEM_BUS,
215 CONFIG_SYS_PCIE1_MEM_PHYS,
216 CONFIG_SYS_PCIE1_MEM_SIZE,
221 CONFIG_SYS_PCIE1_IO_BUS,
222 CONFIG_SYS_PCIE1_IO_PHYS,
223 CONFIG_SYS_PCIE1_IO_SIZE,
226 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
227 /* outbound memory */
229 CONFIG_SYS_PCIE1_MEM_BUS2,
230 CONFIG_SYS_PCIE1_MEM_PHYS2,
231 CONFIG_SYS_PCIE1_MEM_SIZE2,
234 hose->region_count = r - hose->regions;
235 hose->first_busno=first_free_busno;
237 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
241 first_free_busno=hose->last_busno+1;
242 printf(" PCIE1 on bus %02x - %02x\n",
243 hose->first_busno,hose->last_busno);
246 printf (" PCIE1: disabled\n");
251 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
256 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
257 struct pci_controller *hose = &pcie2_hose;
258 int pcie_ep = (host_agent == 3);
259 int pcie_configured = io_sel >= 4;
260 struct pci_region *r = hose->regions;
262 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
263 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
264 pcie_ep ? "End Point" : "Root Complex",
266 if (pci->pme_msg_det) {
267 pci->pme_msg_det = 0xffffffff;
268 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
273 r += fsl_pci_setup_inbound_windows(r);
275 /* outbound memory */
277 CONFIG_SYS_PCIE2_MEM_BUS,
278 CONFIG_SYS_PCIE2_MEM_PHYS,
279 CONFIG_SYS_PCIE2_MEM_SIZE,
284 CONFIG_SYS_PCIE2_IO_BUS,
285 CONFIG_SYS_PCIE2_IO_PHYS,
286 CONFIG_SYS_PCIE2_IO_SIZE,
289 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
290 /* outbound memory */
292 CONFIG_SYS_PCIE2_MEM_BUS2,
293 CONFIG_SYS_PCIE2_MEM_PHYS2,
294 CONFIG_SYS_PCIE2_MEM_SIZE2,
297 hose->region_count = r - hose->regions;
298 hose->first_busno=first_free_busno;
299 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
302 first_free_busno=hose->last_busno+1;
303 printf (" PCIE2 on bus %02x - %02x\n",
304 hose->first_busno,hose->last_busno);
307 printf (" PCIE2: disabled\n");
312 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
318 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
319 struct pci_controller *hose = &pci1_hose;
320 struct pci_region *r = hose->regions;
322 uint pci_agent = (host_agent == 6);
323 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
325 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
326 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
329 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
330 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
332 (pci_speed == 33333000) ? "33" :
333 (pci_speed == 66666000) ? "66" : "unknown",
334 pci_clk_sel ? "sync" : "async",
335 pci_agent ? "agent" : "host",
336 pci_arb ? "arbiter" : "external-arbiter",
341 r += fsl_pci_setup_inbound_windows(r);
343 /* outbound memory */
345 CONFIG_SYS_PCI1_MEM_BUS,
346 CONFIG_SYS_PCI1_MEM_PHYS,
347 CONFIG_SYS_PCI1_MEM_SIZE,
352 CONFIG_SYS_PCI1_IO_BUS,
353 CONFIG_SYS_PCI1_IO_PHYS,
354 CONFIG_SYS_PCI1_IO_SIZE,
357 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
358 /* outbound memory */
360 CONFIG_SYS_PCIE3_MEM_BUS2,
361 CONFIG_SYS_PCIE3_MEM_PHYS2,
362 CONFIG_SYS_PCIE3_MEM_SIZE2,
365 hose->region_count = r - hose->regions;
366 hose->first_busno=first_free_busno;
367 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
370 first_free_busno=hose->last_busno+1;
371 printf ("PCI on bus %02x - %02x\n",
372 hose->first_busno,hose->last_busno);
374 printf (" PCI: disabled\n");
378 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
383 int last_stage_init(void)
390 get_board_sys_clk(ulong dummy)
392 u8 i, go_bit, rd_clks;
395 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
398 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
402 * Only if both go bit and the SCLK bit in VCFGEN0 are set
403 * should we be using the AUX register. Remember, we also set the
404 * GO bit to boot from the alternate bank on the on-board flash
409 i = in8(PIXIS_BASE + PIXIS_AUX);
411 i = in8(PIXIS_BASE + PIXIS_SPD);
413 i = in8(PIXIS_BASE + PIXIS_SPD);
448 int board_eth_init(bd_t *bis)
450 #ifdef CONFIG_TSEC_ENET
451 struct tsec_info_struct tsec_info[2];
452 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
453 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
457 SET_STD_TSEC_INFO(tsec_info[num], 1);
458 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
459 tsec_info[num].flags |= TSEC_SGMII;
463 SET_STD_TSEC_INFO(tsec_info[num], 3);
464 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
465 tsec_info[num].flags |= TSEC_SGMII;
470 printf("No TSECs initialized\n");
476 fsl_sgmii_riser_init(tsec_info, num);
479 tsec_eth_init(bis, tsec_info, num);
481 return pci_eth_init(bis);
484 #if defined(CONFIG_OF_BOARD_SETUP)
485 void ft_board_setup(void *blob, bd_t *bd)
487 ft_cpu_setup(blob, bd);
491 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
494 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
497 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
500 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
502 #ifdef CONFIG_FSL_SGMII_RISER
503 fsl_sgmii_riser_fdt_fixup(blob);