2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42 extern void ddr_enable_ecc(unsigned int dram_size);
47 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
49 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
51 if ((uint)&gur->porpllsr != 0xe00e0000) {
52 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
54 printf ("Board: MPC8544DS, System ID: 0x%02x, "
55 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
56 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
57 in8(PIXIS_BASE + PIXIS_PVER));
59 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
60 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
61 ecm->eedr = 0xffffffff; /* Clear ecm errors */
62 ecm->eeer = 0xffffffff; /* Enable ecm errors */
68 initdram(int board_type)
72 puts("Initializing\n");
74 dram_size = fsl_ddr_sdram();
76 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
78 dram_size *= 0x100000;
80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
82 * Initialize and enable DDR ECC.
84 ddr_enable_ecc(dram_size);
91 static struct pci_controller pci1_hose;
95 static struct pci_controller pcie1_hose;
99 static struct pci_controller pcie2_hose;
103 static struct pci_controller pcie3_hose;
106 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
107 extern void fsl_pci_init(struct pci_controller *hose);
109 int first_free_busno=0;
114 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
115 uint devdisr = gur->devdisr;
116 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
117 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
119 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
120 devdisr, io_sel, host_agent);
123 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
124 printf (" eTSEC1 is in sgmii mode.\n");
125 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
126 printf (" eTSEC3 is in sgmii mode.\n");
131 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
132 struct pci_controller *hose = &pcie3_hose;
133 int pcie_ep = (host_agent == 1);
134 int pcie_configured = io_sel >= 1;
135 struct pci_region *r = hose->regions;
137 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
138 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
139 pcie_ep ? "End Point" : "Root Complex",
141 if (pci->pme_msg_det) {
142 pci->pme_msg_det = 0xffffffff;
143 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
148 r += fsl_pci_setup_inbound_windows(r);
150 /* outbound memory */
152 CONFIG_SYS_PCIE3_MEM_BASE,
153 CONFIG_SYS_PCIE3_MEM_PHYS,
154 CONFIG_SYS_PCIE3_MEM_SIZE,
159 CONFIG_SYS_PCIE3_IO_BASE,
160 CONFIG_SYS_PCIE3_IO_PHYS,
161 CONFIG_SYS_PCIE3_IO_SIZE,
164 #ifdef CONFIG_SYS_PCIE3_MEM_BASE2
165 /* outbound memory */
167 CONFIG_SYS_PCIE3_MEM_BASE2,
168 CONFIG_SYS_PCIE3_MEM_PHYS2,
169 CONFIG_SYS_PCIE3_MEM_SIZE2,
172 hose->region_count = r - hose->regions;
173 hose->first_busno=first_free_busno;
174 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
178 first_free_busno=hose->last_busno+1;
179 printf (" PCIE3 on bus %02x - %02x\n",
180 hose->first_busno,hose->last_busno);
183 * Activate ULI1575 legacy chip by performing a fake
184 * memory access. Needed to make ULI RTC work.
186 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
188 printf (" PCIE3: disabled\n");
193 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
198 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
199 struct pci_controller *hose = &pcie1_hose;
200 int pcie_ep = (host_agent == 5);
201 int pcie_configured = io_sel & 6;
202 struct pci_region *r = hose->regions;
204 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
205 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
206 pcie_ep ? "End Point" : "Root Complex",
208 if (pci->pme_msg_det) {
209 pci->pme_msg_det = 0xffffffff;
210 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
215 r += fsl_pci_setup_inbound_windows(r);
217 /* outbound memory */
219 CONFIG_SYS_PCIE1_MEM_BASE,
220 CONFIG_SYS_PCIE1_MEM_PHYS,
221 CONFIG_SYS_PCIE1_MEM_SIZE,
226 CONFIG_SYS_PCIE1_IO_BASE,
227 CONFIG_SYS_PCIE1_IO_PHYS,
228 CONFIG_SYS_PCIE1_IO_SIZE,
231 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
232 /* outbound memory */
234 CONFIG_SYS_PCIE1_MEM_BASE2,
235 CONFIG_SYS_PCIE1_MEM_PHYS2,
236 CONFIG_SYS_PCIE1_MEM_SIZE2,
239 hose->region_count = r - hose->regions;
240 hose->first_busno=first_free_busno;
242 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
246 first_free_busno=hose->last_busno+1;
247 printf(" PCIE1 on bus %02x - %02x\n",
248 hose->first_busno,hose->last_busno);
251 printf (" PCIE1: disabled\n");
256 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
261 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
262 struct pci_controller *hose = &pcie2_hose;
263 int pcie_ep = (host_agent == 3);
264 int pcie_configured = io_sel & 4;
265 struct pci_region *r = hose->regions;
267 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
268 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
269 pcie_ep ? "End Point" : "Root Complex",
271 if (pci->pme_msg_det) {
272 pci->pme_msg_det = 0xffffffff;
273 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
278 r += fsl_pci_setup_inbound_windows(r);
280 /* outbound memory */
282 CONFIG_SYS_PCIE2_MEM_BASE,
283 CONFIG_SYS_PCIE2_MEM_PHYS,
284 CONFIG_SYS_PCIE2_MEM_SIZE,
289 CONFIG_SYS_PCIE2_IO_BASE,
290 CONFIG_SYS_PCIE2_IO_PHYS,
291 CONFIG_SYS_PCIE2_IO_SIZE,
294 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2
295 /* outbound memory */
297 CONFIG_SYS_PCIE2_MEM_BASE2,
298 CONFIG_SYS_PCIE2_MEM_PHYS2,
299 CONFIG_SYS_PCIE2_MEM_SIZE2,
302 hose->region_count = r - hose->regions;
303 hose->first_busno=first_free_busno;
304 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
307 first_free_busno=hose->last_busno+1;
308 printf (" PCIE2 on bus %02x - %02x\n",
309 hose->first_busno,hose->last_busno);
312 printf (" PCIE2: disabled\n");
317 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
323 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
324 struct pci_controller *hose = &pci1_hose;
325 struct pci_region *r = hose->regions;
327 uint pci_agent = (host_agent == 6);
328 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
330 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
331 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
334 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
335 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
337 (pci_speed == 33333000) ? "33" :
338 (pci_speed == 66666000) ? "66" : "unknown",
339 pci_clk_sel ? "sync" : "async",
340 pci_agent ? "agent" : "host",
341 pci_arb ? "arbiter" : "external-arbiter",
346 r += fsl_pci_setup_inbound_windows(r);
348 /* outbound memory */
350 CONFIG_SYS_PCI1_MEM_BASE,
351 CONFIG_SYS_PCI1_MEM_PHYS,
352 CONFIG_SYS_PCI1_MEM_SIZE,
357 CONFIG_SYS_PCI1_IO_BASE,
358 CONFIG_SYS_PCI1_IO_PHYS,
359 CONFIG_SYS_PCI1_IO_SIZE,
362 #ifdef CONFIG_SYS_PCIE3_MEM_BASE2
363 /* outbound memory */
365 CONFIG_SYS_PCIE3_MEM_BASE2,
366 CONFIG_SYS_PCIE3_MEM_PHYS2,
367 CONFIG_SYS_PCIE3_MEM_SIZE2,
370 hose->region_count = r - hose->regions;
371 hose->first_busno=first_free_busno;
372 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
375 first_free_busno=hose->last_busno+1;
376 printf ("PCI on bus %02x - %02x\n",
377 hose->first_busno,hose->last_busno);
379 printf (" PCI: disabled\n");
383 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
388 int last_stage_init(void)
395 get_board_sys_clk(ulong dummy)
397 u8 i, go_bit, rd_clks;
400 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
403 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
407 * Only if both go bit and the SCLK bit in VCFGEN0 are set
408 * should we be using the AUX register. Remember, we also set the
409 * GO bit to boot from the alternate bank on the on-board flash
414 i = in8(PIXIS_BASE + PIXIS_AUX);
416 i = in8(PIXIS_BASE + PIXIS_SPD);
418 i = in8(PIXIS_BASE + PIXIS_SPD);
453 int board_eth_init(bd_t *bis)
455 #ifdef CONFIG_TSEC_ENET
456 struct tsec_info_struct tsec_info[2];
457 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
458 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
462 SET_STD_TSEC_INFO(tsec_info[num], 1);
463 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
464 tsec_info[num].flags |= TSEC_SGMII;
468 SET_STD_TSEC_INFO(tsec_info[num], 3);
469 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
470 tsec_info[num].flags |= TSEC_SGMII;
475 printf("No TSECs initialized\n");
481 fsl_sgmii_riser_init(tsec_info, num);
484 tsec_eth_init(bis, tsec_info, num);
486 return pci_eth_init(bis);
489 #if defined(CONFIG_OF_BOARD_SETUP)
490 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
491 struct pci_controller *hose);
493 void ft_board_setup(void *blob, bd_t *bd)
495 ft_cpu_setup(blob, bd);
499 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
502 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
505 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
508 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);