2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx6-pins.h>
11 #include <asm/arch/clock.h>
12 #include <asm/errno.h>
14 #include <asm/imx-common/iomux-v3.h>
16 #include <fsl_esdhc.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
23 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
24 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
26 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
27 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
28 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
30 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
31 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
35 #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
36 defined(CONFIG_DDR_32BIT)
37 gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
39 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
45 iomux_v3_cfg_t const uart4_pads[] = {
46 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
47 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
50 iomux_v3_cfg_t const usdhc3_pads[] = {
51 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
52 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
53 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
54 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
64 iomux_v3_cfg_t const usdhc4_pads[] = {
65 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
67 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 iomux_v3_cfg_t const enet_pads[] = {
78 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 static void setup_iomux_uart(void)
98 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
101 static void setup_iomux_enet(void)
103 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
106 #ifdef CONFIG_FSL_ESDHC
107 struct fsl_esdhc_cfg usdhc_cfg[2] = {
112 int board_mmc_getcd(struct mmc *mmc)
114 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
117 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
118 gpio_direction_input(IMX_GPIO_NR(6, 11));
119 ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
120 } else /* Don't have the CD GPIO pin on board */
126 int board_mmc_init(bd_t *bis)
131 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
132 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
134 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
137 imx_iomux_v3_setup_multiple_pads(
138 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
141 imx_iomux_v3_setup_multiple_pads(
142 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
145 printf("Warning: you configured more USDHC controllers"
146 "(%d) then supported by the board (%d)\n",
147 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
151 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
160 #define MII_MMD_ACCESS_CTRL_REG 0xd
161 #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
162 #define MII_DBG_PORT_REG 0x1d
163 #define MII_DBG_PORT2_REG 0x1e
165 int fecmxc_mii_postcall(int phy)
170 * Due to the i.MX6Q Armadillo2 board HW design,there is
171 * no 125Mhz clock input from SOC. In order to use RGMII,
172 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
174 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
175 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
176 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
177 miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
180 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
182 /* For the RGMII phy, we need enable tx clock delay */
183 miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
184 miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
186 miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
188 miiphy_write("FEC", phy, MII_BMCR, 0xa100);
193 int board_eth_init(bd_t *bis)
195 struct eth_device *dev;
196 int ret = cpu_eth_init(bis);
201 dev = eth_get_dev_by_name("FEC");
203 printf("FEC MXC: Unable to get FEC device entry\n");
207 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
209 printf("FEC MXC: Unable to register FEC mii postcall\n");
216 int board_early_init_f(void)
226 /* address of boot parameters */
227 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
235 puts("Board: MX6DL-Armadillo2\n");
237 puts("Board: MX6Q-Armadillo2\n");