board/freescale/mx6qsabreauto/mx6qsabreauto.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/mxc_i2c.h>
  19 #include <asm/imx-common/boot_mode.h>
  20 #include <asm/imx-common/spi.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc.h>
  23 #include <miiphy.h>
  24 #include <netdev.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <i2c.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/imx-common/video.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <pca953x.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  35         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  39         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  44
  45 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  47         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  48
  49 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  50
  51 int dram_init(void)
  52 {
  53         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  54
  55         return 0;
  56 }
  57
  58 static iomux_v3_cfg_t const uart4_pads[] = {
  59         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  60         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  61 };
  62
  63 static iomux_v3_cfg_t const enet_pads[] = {
  64         MX6_PAD_KEY_COL1__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_KEY_COL2__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79 };
  80
  81 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  82 static struct i2c_pads_info i2c_pad_info1 = {
  83         .scl = {
  84                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  85                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  86                 .gp = IMX_GPIO_NR(2, 30)
  87         },
  88         .sda = {
  89                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  90                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  91                 .gp = IMX_GPIO_NR(4, 13)
  92         }
  93 };
  94
  95 /*
  96  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  97  * Compass Sensor, Accelerometer, Res Touch
  98  */
  99 static struct i2c_pads_info i2c_pad_info2 = {
 100         .scl = {
 101                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
 102                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 103                 .gp = IMX_GPIO_NR(1, 3)
 104         },
 105         .sda = {
 106                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 107                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 108                 .gp = IMX_GPIO_NR(3, 18)
 109         }
 110 };
 111
 112 static iomux_v3_cfg_t const i2c3_pads[] = {
 113         MX6_PAD_EIM_A24__GPIO5_IO04             | MUX_PAD_CTRL(NO_PAD_CTRL),
 114 };
 115
 116 static iomux_v3_cfg_t const port_exp[] = {
 117         MX6_PAD_SD2_DAT0__GPIO1_IO15            | MUX_PAD_CTRL(NO_PAD_CTRL),
 118 };
 119
 120 /*Define for building port exp gpio, pin starts from 0*/
 121 #define PORTEXP_IO_NR(chip, pin) \
 122         ((chip << 5) + pin)
 123
 124 /*Get the chip addr from a ioexp gpio*/
 125 #define PORTEXP_IO_TO_CHIP(gpio_nr) \
 126         (gpio_nr >> 5)
 127
 128 /*Get the pin number from a ioexp gpio*/
 129 #define PORTEXP_IO_TO_PIN(gpio_nr) \
 130         (gpio_nr & 0x1f)
 131
 132 static int port_exp_direction_output(unsigned gpio, int value)
 133 {
 134         int ret;
 135
 136         i2c_set_bus_num(2);
 137         ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
 138         if (ret)
 139                 return ret;
 140
 141         ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
 142                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 143                 (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
 144
 145         if (ret)
 146                 return ret;
 147
 148         ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
 149                 (1 << PORTEXP_IO_TO_PIN(gpio)),
 150                 (value << PORTEXP_IO_TO_PIN(gpio)));
 151
 152         if (ret)
 153                 return ret;
 154
 155         return 0;
 156 }
 157
 158 static void setup_iomux_enet(void)
 159 {
 160         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 161 }
 162
 163 static iomux_v3_cfg_t const usdhc3_pads[] = {
 164         MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD3_DAT1__SD3_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD3_DAT2__SD3_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_SD3_DAT3__SD3_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         MX6_PAD_SD3_DAT4__SD3_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_SD3_DAT5__SD3_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         MX6_PAD_SD3_DAT6__SD3_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         MX6_PAD_SD3_DAT7__SD3_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174         MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
 176 };
 177
 178 static void setup_iomux_uart(void)
 179 {
 180         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 181 }
 182
 183 #ifdef CONFIG_FSL_ESDHC
 184 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 185         {USDHC3_BASE_ADDR},
 186 };
 187
 188 int board_mmc_getcd(struct mmc *mmc)
 189 {
 190         gpio_direction_input(IMX_GPIO_NR(6, 15));
 191         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 192 }
 193
 194 int board_mmc_init(bd_t *bis)
 195 {
 196         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 197
 198         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 199         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 200 }
 201 #endif
 202
 203 int mx6_rgmii_rework(struct phy_device *phydev)
 204 {
 205         unsigned short val;
 206
 207         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 208         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 209         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 210         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 211
 212         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 213         val &= 0xffe3;
 214         val |= 0x18;
 215         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 216
 217         /* introduce tx clock delay */
 218         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 219         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 220         val |= 0x0100;
 221         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 222
 223         return 0;
 224 }
 225
 226 int board_phy_config(struct phy_device *phydev)
 227 {
 228         mx6_rgmii_rework(phydev);
 229
 230         if (phydev->drv->config)
 231                 phydev->drv->config(phydev);
 232
 233         return 0;
 234 }
 235
 236 int board_eth_init(bd_t *bis)
 237 {
 238         setup_iomux_enet();
 239
 240         return cpu_eth_init(bis);
 241 }
 242
 243 #define BOARD_REV_B  0x200
 244 #define BOARD_REV_A  0x100
 245
 246 static int mx6sabre_rev(void)
 247 {
 248         /*
 249          * Get Board ID information from OCOTP_GP1[15:8]
 250          * i.MX6Q ARD RevA: 0x01
 251          * i.MX6Q ARD RevB: 0x02
 252          */
 253         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 254         struct fuse_bank *bank = &ocotp->bank[4];
 255         struct fuse_bank4_regs *fuse =
 256                         (struct fuse_bank4_regs *)bank->fuse_regs;
 257         int reg = readl(&fuse->gp1);
 258         int ret;
 259
 260         switch (reg >> 8 & 0x0F) {
 261         case 0x02:
 262                 ret = BOARD_REV_B;
 263                 break;
 264         case 0x01:
 265         default:
 266                 ret = BOARD_REV_A;
 267                 break;
 268         }
 269
 270         return ret;
 271 }
 272
 273 u32 get_board_rev(void)
 274 {
 275         int rev = mx6sabre_rev();
 276
 277         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 278 }
 279
 280 #if defined(CONFIG_VIDEO_IPUV3)
 281 static void do_enable_hdmi(struct display_info_t const *dev)
 282 {
 283         imx_enable_hdmi_phy();
 284 }
 285
 286 struct display_info_t const displays[] = {{
 287         .bus    = -1,
 288         .addr   = 0,
 289         .pixfmt = IPU_PIX_FMT_RGB24,
 290         .detect = detect_hdmi,
 291         .enable = do_enable_hdmi,
 292         .mode   = {
 293                 .name           = "HDMI",
 294                 .refresh        = 60,
 295                 .xres           = 1024,
 296                 .yres           = 768,
 297                 .pixclock       = 15385,
 298                 .left_margin    = 220,
 299                 .right_margin   = 40,
 300                 .upper_margin   = 21,
 301                 .lower_margin   = 7,
 302                 .hsync_len      = 60,
 303                 .vsync_len      = 10,
 304                 .sync           = FB_SYNC_EXT,
 305                 .vmode          = FB_VMODE_NONINTERLACED,
 306 } } };
 307 size_t display_count = ARRAY_SIZE(displays);
 308
 309 static void setup_display(void)
 310 {
 311         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 312         int reg;
 313
 314         enable_ipu_clock();
 315         imx_setup_hdmi();
 316
 317         reg = readl(&mxc_ccm->chsccdr);
 318         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 319                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 320         writel(reg, &mxc_ccm->chsccdr);
 321 }
 322 #endif /* CONFIG_VIDEO_IPUV3 */
 323
 324 /*
 325  * Do not overwrite the console
 326  * Use always serial for U-Boot console
 327  */
 328 int overwrite_console(void)
 329 {
 330         return 1;
 331 }
 332
 333 int board_early_init_f(void)
 334 {
 335         setup_iomux_uart();
 336 #ifdef CONFIG_VIDEO_IPUV3
 337         setup_display();
 338 #endif
 339         return 0;
 340 }
 341
 342 int board_init(void)
 343 {
 344         /* address of boot parameters */
 345         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 346
 347         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 348         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 349         /* I2C 3 Steer */
 350         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 351         imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 352         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 353
 354         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 355         imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
 356
 357         return 0;
 358 }
 359
 360 #ifdef CONFIG_MXC_SPI
 361 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 362 {
 363         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 364 }
 365 #endif
 366
 367 #ifdef CONFIG_CMD_BMODE
 368 static const struct boot_mode board_boot_modes[] = {
 369         /* 4 bit bus width */
 370         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 371         {NULL,   0},
 372 };
 373 #endif
 374
 375 int board_late_init(void)
 376 {
 377 #ifdef CONFIG_CMD_BMODE
 378         add_board_boot_modes(board_boot_modes);
 379 #endif
 380
 381         return 0;
 382 }
 383
 384 int checkboard(void)
 385 {
 386         int rev = mx6sabre_rev();
 387         char *revname;
 388
 389         switch (rev) {
 390         case BOARD_REV_B:
 391                 revname = "B";
 392                 break;
 393         case BOARD_REV_A:
 394         default:
 395                 revname = "A";
 396                 break;
 397         }
 398
 399         printf("Board: MX6Q-Sabreauto rev%s\n", revname);
 400
 401         return 0;
 402 }
 403
 404 #ifdef CONFIG_USB_EHCI_MX6
 405 #define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
 406 #define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
 407
 408 iomux_v3_cfg_t const usb_otg_pads[] = {
 409         MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 410 };
 411
 412 int board_ehci_hcd_init(int port)
 413 {
 414         switch (port) {
 415         case 0:
 416                 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 417                         ARRAY_SIZE(usb_otg_pads));
 418
 419                 /*
 420                   * Set daisy chain for otg_pin_id on 6q.
 421                  *  For 6dl, this bit is reserved.
 422                  */
 423                 imx_iomux_set_gpr_register(1, 13, 1, 0);
 424                 break;
 425         case 1:
 426                 break;
 427         default:
 428                 printf("MXC USB port %d not yet supported\n", port);
 429                 return -EINVAL;
 430         }
 431         return 0;
 432 }
 433
 434 int board_ehci_power(int port, int on)
 435 {
 436         switch (port) {
 437         case 0:
 438                 if (on)
 439                         port_exp_direction_output(USB_OTG_PWR, 1);
 440                 else
 441                         port_exp_direction_output(USB_OTG_PWR, 0);
 442                 break;
 443         case 1:
 444                 if (on)
 445                         port_exp_direction_output(USB_HOST1_PWR, 1);
 446                 else
 447                         port_exp_direction_output(USB_HOST1_PWR, 0);
 448                 break;
 449         default:
 450                 printf("MXC USB port %d not yet supported\n", port);
 451                 return -EINVAL;
 452         }
 453
 454         return 0;
 455 }
 456 #endif