2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/iomux.h>
28 #include <asm/arch/mx6q_pins.h>
29 #include <asm/errno.h>
31 #include <asm/imx-common/iomux-v3.h>
32 #include <asm/imx-common/mxc_i2c.h>
33 #include <asm/imx-common/boot_mode.h>
35 #include <fsl_esdhc.h>
41 #include <ipu_pixfmt.h>
42 #include <asm/arch/crm_regs.h>
43 #include <asm/arch/mxc_hdmi.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
50 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
53 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
54 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
56 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
59 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
65 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
66 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
67 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
71 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
76 iomux_v3_cfg_t const uart1_pads[] = {
77 MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
81 iomux_v3_cfg_t const uart2_pads[] = {
82 MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
86 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
89 struct i2c_pads_info i2c_pad_info0 = {
91 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
92 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
93 .gp = IMX_GPIO_NR(3, 21)
96 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
97 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
98 .gp = IMX_GPIO_NR(3, 28)
102 /* I2C2 Camera, MIPI */
103 struct i2c_pads_info i2c_pad_info1 = {
105 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
106 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
107 .gp = IMX_GPIO_NR(4, 12)
110 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
111 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
112 .gp = IMX_GPIO_NR(4, 13)
116 /* I2C3, J15 - RGB connector */
117 struct i2c_pads_info i2c_pad_info2 = {
119 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
120 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
121 .gp = IMX_GPIO_NR(1, 5)
124 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
125 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
126 .gp = IMX_GPIO_NR(7, 11)
130 iomux_v3_cfg_t const usdhc3_pads[] = {
131 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
140 iomux_v3_cfg_t const usdhc4_pads[] = {
141 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
150 iomux_v3_cfg_t const enet_pads1[] = {
151 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
152 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
153 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
154 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
155 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
156 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
157 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
158 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
159 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 /* pin 35 - 1 (PHY_AD2) on reset */
161 MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
162 /* pin 32 - 1 - (MODE0) all */
163 MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
164 /* pin 31 - 1 - (MODE1) all */
165 MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
166 /* pin 28 - 1 - (MODE2) all */
167 MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
168 /* pin 27 - 1 - (MODE3) all */
169 MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
171 MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 /* pin 42 PHY nRST */
173 MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 iomux_v3_cfg_t const enet_pads2[] = {
177 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
178 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
179 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
180 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
181 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
182 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
185 /* Button assignments for J14 */
186 static iomux_v3_cfg_t const button_pads[] = {
188 MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
190 MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
191 /* Labelled Search (mapped to Power under Android) */
192 MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
194 MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
196 MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
198 MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
201 static void setup_iomux_enet(void)
203 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
204 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
205 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
206 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
207 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
208 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
209 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
210 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
212 /* Need delay 10ms according to KSZ9021 spec */
214 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
216 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
219 iomux_v3_cfg_t const usb_pads[] = {
220 MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
223 static void setup_iomux_uart(void)
225 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
226 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
229 #ifdef CONFIG_USB_EHCI_MX6
230 int board_ehci_hcd_init(int port)
232 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
235 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
237 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
243 #ifdef CONFIG_FSL_ESDHC
244 struct fsl_esdhc_cfg usdhc_cfg[2] = {
249 int board_mmc_getcd(struct mmc *mmc)
251 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
254 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
255 gpio_direction_input(IMX_GPIO_NR(7, 0));
256 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
258 gpio_direction_input(IMX_GPIO_NR(2, 6));
259 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
265 int board_mmc_init(bd_t *bis)
270 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
271 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
273 usdhc_cfg[0].max_bus_width = 4;
274 usdhc_cfg[1].max_bus_width = 4;
276 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
279 imx_iomux_v3_setup_multiple_pads(
280 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
283 imx_iomux_v3_setup_multiple_pads(
284 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
287 printf("Warning: you configured more USDHC controllers"
288 "(%d) then supported by the board (%d)\n",
289 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
293 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
300 #ifdef CONFIG_MXC_SPI
301 iomux_v3_cfg_t const ecspi1_pads[] = {
303 MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
304 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
305 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
306 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
311 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
312 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
313 ARRAY_SIZE(ecspi1_pads));
317 int board_phy_config(struct phy_device *phydev)
319 /* min rx data delay */
320 ksz9021_phy_extended_write(phydev,
321 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
322 /* min tx data delay */
323 ksz9021_phy_extended_write(phydev,
324 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
325 /* max rx/tx clock delay, min rx/tx control */
326 ksz9021_phy_extended_write(phydev,
327 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
328 if (phydev->drv->config)
329 phydev->drv->config(phydev);
334 int board_eth_init(bd_t *bis)
336 uint32_t base = IMX_FEC_BASE;
337 struct mii_dev *bus = NULL;
338 struct phy_device *phydev = NULL;
343 #ifdef CONFIG_FEC_MXC
344 bus = fec_get_miibus(base, -1);
347 /* scan phy 4,5,6,7 */
348 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
353 printf("using phy at %d\n", phydev->addr);
354 ret = fec_probe(bis, -1, base, bus, phydev);
356 printf("FEC MXC: %s:failed\n", __func__);
364 static void setup_buttons(void)
366 imx_iomux_v3_setup_multiple_pads(button_pads,
367 ARRAY_SIZE(button_pads));
370 #ifdef CONFIG_CMD_SATA
374 struct iomuxc_base_regs *const iomuxc_regs
375 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
376 int ret = enable_sata_clock();
380 clrsetbits_le32(&iomuxc_regs->gpr[13],
381 IOMUXC_GPR13_SATA_MASK,
382 IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
383 |IOMUXC_GPR13_SATA_PHY_7_SATA2M
384 |IOMUXC_GPR13_SATA_SPEED_3G
385 |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
386 |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
387 |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
388 |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
389 |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
390 |IOMUXC_GPR13_SATA_PHY_1_SLOW);
396 #if defined(CONFIG_VIDEO_IPUV3)
398 static iomux_v3_cfg_t const backlight_pads[] = {
399 /* Backlight on RGB connector: J15 */
400 MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
401 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
403 /* Backlight on LVDS connector: J6 */
404 MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
405 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
408 static iomux_v3_cfg_t const rgb_pads[] = {
409 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
410 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
411 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
412 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
413 MX6_PAD_DI0_PIN4__GPIO_4_20,
414 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
415 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
416 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
417 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
418 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
419 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
420 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
421 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
422 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
423 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
424 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
425 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
426 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
427 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
428 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
429 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
430 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
431 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
432 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
433 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
434 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
435 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
436 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
437 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
440 struct display_info_t {
444 int (*detect)(struct display_info_t const *dev);
445 void (*enable)(struct display_info_t const *dev);
446 struct fb_videomode mode;
450 static int detect_hdmi(struct display_info_t const *dev)
452 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
453 return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
456 static void enable_hdmi(struct display_info_t const *dev)
458 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
460 printf("%s: setup HDMI monitor\n", __func__);
461 reg = readb(&hdmi->phy_conf0);
462 reg |= HDMI_PHY_CONF0_PDZ_MASK;
463 writeb(reg, &hdmi->phy_conf0);
466 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
467 writeb(reg, &hdmi->phy_conf0);
469 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
470 writeb(reg, &hdmi->phy_conf0);
471 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
474 static int detect_i2c(struct display_info_t const *dev)
476 return ((0 == i2c_set_bus_num(dev->bus))
478 (0 == i2c_probe(dev->addr)));
481 static void enable_lvds(struct display_info_t const *dev)
483 struct iomuxc *iomux = (struct iomuxc *)
485 u32 reg = readl(&iomux->gpr[2]);
486 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
487 writel(reg, &iomux->gpr[2]);
488 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
491 static void enable_rgb(struct display_info_t const *dev)
493 imx_iomux_v3_setup_multiple_pads(
495 ARRAY_SIZE(rgb_pads));
496 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
499 static struct display_info_t const displays[] = {{
502 .pixfmt = IPU_PIX_FMT_RGB24,
503 .detect = detect_hdmi,
504 .enable = enable_hdmi,
518 .vmode = FB_VMODE_NONINTERLACED
522 .pixfmt = IPU_PIX_FMT_LVDS666,
523 .detect = detect_i2c,
524 .enable = enable_lvds,
526 .name = "Hannstar-XGA",
538 .vmode = FB_VMODE_NONINTERLACED
542 .pixfmt = IPU_PIX_FMT_LVDS666,
543 .detect = detect_i2c,
544 .enable = enable_lvds,
546 .name = "wsvga-lvds",
558 .vmode = FB_VMODE_NONINTERLACED
562 .pixfmt = IPU_PIX_FMT_RGB666,
563 .detect = detect_i2c,
564 .enable = enable_rgb,
578 .vmode = FB_VMODE_NONINTERLACED
581 int board_video_skip(void)
585 char const *panel = getenv("panel");
587 for (i = 0; i < ARRAY_SIZE(displays); i++) {
588 struct display_info_t const *dev = displays+i;
589 if (dev->detect(dev)) {
590 panel = dev->mode.name;
591 printf("auto-detected panel %s\n", panel);
596 panel = displays[0].mode.name;
597 printf("No panel detected: default to %s\n", panel);
600 for (i = 0; i < ARRAY_SIZE(displays); i++) {
601 if (!strcmp(panel, displays[i].mode.name))
605 if (i < ARRAY_SIZE(displays)) {
606 ret = ipuv3_fb_init(&displays[i].mode, 0,
609 displays[i].enable(displays+i);
610 printf("Display: %s (%ux%u)\n",
611 displays[i].mode.name,
612 displays[i].mode.xres,
613 displays[i].mode.yres);
615 printf("LCD %s cannot be configured: %d\n",
616 displays[i].mode.name, ret);
618 printf("unsupported panel %s\n", panel);
624 static void setup_display(void)
626 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
627 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
628 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
629 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
633 /* Turn on LDB0,IPU,IPU DI0 clocks */
634 reg = __raw_readl(&mxc_ccm->CCGR3);
635 reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
636 |MXC_CCM_CCGR3_LDB_DI0_MASK;
637 writel(reg, &mxc_ccm->CCGR3);
639 /* Turn on HDMI PHY clock */
640 reg = __raw_readl(&mxc_ccm->CCGR2);
641 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
642 |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
643 writel(reg, &mxc_ccm->CCGR2);
645 /* clear HDMI PHY reset */
646 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
648 /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
649 writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
650 writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
652 /* set LDB0, LDB1 clk select to 011/011 */
653 reg = readl(&mxc_ccm->cs2cdr);
654 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
655 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
656 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
657 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
658 writel(reg, &mxc_ccm->cs2cdr);
660 reg = readl(&mxc_ccm->cscmr2);
661 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
662 writel(reg, &mxc_ccm->cscmr2);
664 reg = readl(&mxc_ccm->chsccdr);
665 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
666 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
667 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
668 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
669 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
670 |(CHSCCDR_PODF_DIVIDE_BY_3
671 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
672 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
673 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
674 writel(reg, &mxc_ccm->chsccdr);
676 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
677 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
678 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
679 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
680 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
681 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
682 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
683 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
684 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
685 writel(reg, &iomux->gpr[2]);
687 reg = readl(&iomux->gpr[3]);
688 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
689 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
690 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
691 writel(reg, &iomux->gpr[3]);
693 /* backlights off until needed */
694 imx_iomux_v3_setup_multiple_pads(backlight_pads,
695 ARRAY_SIZE(backlight_pads));
696 gpio_direction_input(LVDS_BACKLIGHT_GP);
697 gpio_direction_input(RGB_BACKLIGHT_GP);
701 int board_early_init_f(void)
706 #if defined(CONFIG_VIDEO_IPUV3)
713 * Do not overwrite the console
714 * Use always serial for U-Boot console
716 int overwrite_console(void)
723 /* address of boot parameters */
724 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
726 #ifdef CONFIG_MXC_SPI
729 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
730 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
731 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
733 #ifdef CONFIG_CMD_SATA
742 puts("Board: MX6Q-Sabre Lite\n");
753 static struct button_key const buttons[] = {
754 {"back", IMX_GPIO_NR(2, 2), 'B'},
755 {"home", IMX_GPIO_NR(2, 4), 'H'},
756 {"menu", IMX_GPIO_NR(2, 1), 'M'},
757 {"search", IMX_GPIO_NR(2, 3), 'S'},
758 {"volup", IMX_GPIO_NR(7, 13), 'V'},
759 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
763 * generate a null-terminated string containing the buttons pressed
764 * returns number of keys pressed
766 static int read_keys(char *buf)
768 int i, numpressed = 0;
769 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
770 if (!gpio_get_value(buttons[i].gpnum))
771 buf[numpressed++] = buttons[i].ident;
773 buf[numpressed] = '\0';
777 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
779 char envvalue[ARRAY_SIZE(buttons)+1];
780 int numpressed = read_keys(envvalue);
781 setenv("keybd", envvalue);
782 return numpressed == 0;
787 "Tests for keypresses, sets 'keybd' environment variable",
788 "Returns 0 (true) to shell if key is pressed."
791 #ifdef CONFIG_PREBOOT
792 static char const kbd_magic_prefix[] = "key_magic";
793 static char const kbd_command_prefix[] = "key_cmd";
795 static void preboot_keys(void)
798 char keypress[ARRAY_SIZE(buttons)+1];
799 numpressed = read_keys(keypress);
801 char *kbd_magic_keys = getenv("magic_keys");
804 * loop over all magic keys
806 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
808 char magic[sizeof(kbd_magic_prefix) + 1];
809 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
810 keys = getenv(magic);
812 if (!strcmp(keys, keypress))
817 char cmd_name[sizeof(kbd_command_prefix) + 1];
819 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
820 cmd = getenv(cmd_name);
822 setenv("preboot", cmd);
830 #ifdef CONFIG_CMD_BMODE
831 static const struct boot_mode board_boot_modes[] = {
832 /* 4 bit bus width */
833 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
834 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
839 int misc_init_r(void)
841 #ifdef CONFIG_PREBOOT
845 #ifdef CONFIG_CMD_BMODE
846 add_board_boot_modes(board_boot_modes);