board/freescale/mx6qsabrelite/mx6qsabrelite.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/arch/mx6q_pins.h>
  29 #include <asm/errno.h>
  30 #include <asm/gpio.h>
  31 #include <asm/imx-common/iomux-v3.h>
  32 #include <asm/imx-common/mxc_i2c.h>
  33 #include <asm/imx-common/boot_mode.h>
  34 #include <mmc.h>
  35 #include <fsl_esdhc.h>
  36 #include <malloc.h>
  37 #include <micrel.h>
  38 #include <miiphy.h>
  39 #include <netdev.h>
  40 #include <linux/fb.h>
  41 #include <ipu_pixfmt.h>
  42 #include <asm/arch/crm_regs.h>
  43 #include <asm/arch/mxc_hdmi.h>
  44 #include <i2c.h>
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
  49         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |              \
  50         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  53         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |              \
  54         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  57         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  58         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  59
  60 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  61         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  62         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  63
  64 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  65         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  66         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  67
  68 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  69         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  70         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  71         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  72
  73 int dram_init(void)
  74 {
  75         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  76
  77         return 0;
  78 }
  79
  80 iomux_v3_cfg_t const uart1_pads[] = {
  81         MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  82         MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  83 };
  84
  85 iomux_v3_cfg_t const uart2_pads[] = {
  86         MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  87         MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  88 };
  89
  90 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  91
  92 /* I2C1, SGTL5000 */
  93 struct i2c_pads_info i2c_pad_info0 = {
  94         .scl = {
  95                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  96                 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
  97                 .gp = IMX_GPIO_NR(3, 21)
  98         },
  99         .sda = {
 100                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
 101                 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
 102                 .gp = IMX_GPIO_NR(3, 28)
 103         }
 104 };
 105
 106 /* I2C2 Camera, MIPI */
 107 struct i2c_pads_info i2c_pad_info1 = {
 108         .scl = {
 109                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 110                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
 111                 .gp = IMX_GPIO_NR(4, 12)
 112         },
 113         .sda = {
 114                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 115                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
 116                 .gp = IMX_GPIO_NR(4, 13)
 117         }
 118 };
 119
 120 /* I2C3, J15 - RGB connector */
 121 struct i2c_pads_info i2c_pad_info2 = {
 122         .scl = {
 123                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 124                 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
 125                 .gp = IMX_GPIO_NR(1, 5)
 126         },
 127         .sda = {
 128                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 129                 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
 130                 .gp = IMX_GPIO_NR(7, 11)
 131         }
 132 };
 133
 134 iomux_v3_cfg_t const usdhc3_pads[] = {
 135         MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 142 };
 143
 144 iomux_v3_cfg_t const usdhc4_pads[] = {
 145         MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 152 };
 153
 154 iomux_v3_cfg_t const enet_pads1[] = {
 155         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 157         MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 158         MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         /* pin 35 - 1 (PHY_AD2) on reset */
 165         MX6_PAD_RGMII_RXC__GPIO_6_30            | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         /* pin 32 - 1 - (MODE0) all */
 167         MX6_PAD_RGMII_RD0__GPIO_6_25            | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         /* pin 31 - 1 - (MODE1) all */
 169         MX6_PAD_RGMII_RD1__GPIO_6_27            | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         /* pin 28 - 1 - (MODE2) all */
 171         MX6_PAD_RGMII_RD2__GPIO_6_28            | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         /* pin 27 - 1 - (MODE3) all */
 173         MX6_PAD_RGMII_RD3__GPIO_6_29            | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 175         MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         /* pin 42 PHY nRST */
 177         MX6_PAD_EIM_D23__GPIO_3_23              | MUX_PAD_CTRL(NO_PAD_CTRL),
 178 };
 179
 180 iomux_v3_cfg_t const enet_pads2[] = {
 181         MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 182         MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 183         MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 184         MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 185         MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 186         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 187 };
 188
 189 /* Button assignments for J14 */
 190 static iomux_v3_cfg_t const button_pads[] = {
 191         /* Menu */
 192         MX6_PAD_NANDF_D1__GPIO_2_1      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 193         /* Back */
 194         MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 195         /* Labelled Search (mapped to Power under Android) */
 196         MX6_PAD_NANDF_D3__GPIO_2_3      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 197         /* Home */
 198         MX6_PAD_NANDF_D4__GPIO_2_4      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 199         /* Volume Down */
 200         MX6_PAD_GPIO_19__GPIO_4_5       | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 201         /* Volume Up */
 202         MX6_PAD_GPIO_18__GPIO_7_13      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 203 };
 204
 205 static void setup_iomux_enet(void)
 206 {
 207         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 208         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 209         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 210         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 211         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 212         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 213         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 214         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 215
 216         /* Need delay 10ms according to KSZ9021 spec */
 217         udelay(1000 * 10);
 218         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 219
 220         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 221 }
 222
 223 iomux_v3_cfg_t const usb_pads[] = {
 224         MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 225 };
 226
 227 static void setup_iomux_uart(void)
 228 {
 229         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 230         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 231 }
 232
 233 #ifdef CONFIG_USB_EHCI_MX6
 234 int board_ehci_hcd_init(int port)
 235 {
 236         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 237
 238         /* Reset USB hub */
 239         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 240         mdelay(2);
 241         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 242
 243         return 0;
 244 }
 245 #endif
 246
 247 #ifdef CONFIG_FSL_ESDHC
 248 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 249         {USDHC3_BASE_ADDR},
 250         {USDHC4_BASE_ADDR},
 251 };
 252
 253 int board_mmc_getcd(struct mmc *mmc)
 254 {
 255         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 256         int ret;
 257
 258         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 259                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 260                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 261         } else {
 262                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 263                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 264         }
 265
 266         return ret;
 267 }
 268
 269 int board_mmc_init(bd_t *bis)
 270 {
 271         s32 status = 0;
 272         u32 index = 0;
 273
 274         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 275         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 276
 277         usdhc_cfg[0].max_bus_width = 4;
 278         usdhc_cfg[1].max_bus_width = 4;
 279
 280         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 281                 switch (index) {
 282                 case 0:
 283                         imx_iomux_v3_setup_multiple_pads(
 284                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 285                         break;
 286                 case 1:
 287                         imx_iomux_v3_setup_multiple_pads(
 288                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 289                        break;
 290                default:
 291                         printf("Warning: you configured more USDHC controllers"
 292                                "(%d) then supported by the board (%d)\n",
 293                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 294                         return status;
 295                 }
 296
 297                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 298         }
 299
 300         return status;
 301 }
 302 #endif
 303
 304 u32 get_board_rev(void)
 305 {
 306         return 0x63000 ;
 307 }
 308
 309 #ifdef CONFIG_MXC_SPI
 310 iomux_v3_cfg_t const ecspi1_pads[] = {
 311         /* SS1 */
 312         MX6_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 313         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 314         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 315         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 316 };
 317
 318 void setup_spi(void)
 319 {
 320         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 321         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 322                                          ARRAY_SIZE(ecspi1_pads));
 323 }
 324 #endif
 325
 326 int board_phy_config(struct phy_device *phydev)
 327 {
 328         /* min rx data delay */
 329         ksz9021_phy_extended_write(phydev,
 330                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 331         /* min tx data delay */
 332         ksz9021_phy_extended_write(phydev,
 333                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 334         /* max rx/tx clock delay, min rx/tx control */
 335         ksz9021_phy_extended_write(phydev,
 336                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 337         if (phydev->drv->config)
 338                 phydev->drv->config(phydev);
 339
 340         return 0;
 341 }
 342
 343 int board_eth_init(bd_t *bis)
 344 {
 345         uint32_t base = IMX_FEC_BASE;
 346         struct mii_dev *bus = NULL;
 347         struct phy_device *phydev = NULL;
 348         int ret;
 349
 350         setup_iomux_enet();
 351
 352 #ifdef CONFIG_FEC_MXC
 353         bus = fec_get_miibus(base, -1);
 354         if (!bus)
 355                 return 0;
 356         /* scan phy 4,5,6,7 */
 357         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 358         if (!phydev) {
 359                 free(bus);
 360                 return 0;
 361         }
 362         printf("using phy at %d\n", phydev->addr);
 363         ret  = fec_probe(bis, -1, base, bus, phydev);
 364         if (ret) {
 365                 printf("FEC MXC: %s:failed\n", __func__);
 366                 free(phydev);
 367                 free(bus);
 368         }
 369 #endif
 370         return 0;
 371 }
 372
 373 static void setup_buttons(void)
 374 {
 375         imx_iomux_v3_setup_multiple_pads(button_pads,
 376                                          ARRAY_SIZE(button_pads));
 377 }
 378
 379 #ifdef CONFIG_CMD_SATA
 380
 381 int setup_sata(void)
 382 {
 383         struct iomuxc_base_regs *const iomuxc_regs
 384                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 385         int ret = enable_sata_clock();
 386         if (ret)
 387                 return ret;
 388
 389         clrsetbits_le32(&iomuxc_regs->gpr[13],
 390                         IOMUXC_GPR13_SATA_MASK,
 391                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 392                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 393                         |IOMUXC_GPR13_SATA_SPEED_3G
 394                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 395                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 396                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 397                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 398                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 399                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 400
 401         return 0;
 402 }
 403 #endif
 404
 405 #if defined(CONFIG_VIDEO_IPUV3)
 406
 407 static iomux_v3_cfg_t const backlight_pads[] = {
 408         /* Backlight on RGB connector: J15 */
 409         MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 410 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 411
 412         /* Backlight on LVDS connector: J6 */
 413         MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 414 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 415 };
 416
 417 static iomux_v3_cfg_t const rgb_pads[] = {
 418         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 419         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 420         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 421         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 422         MX6_PAD_DI0_PIN4__GPIO_4_20,
 423         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 424         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 425         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 426         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 427         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 428         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 429         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 430         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 431         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 432         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 433         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 434         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 435         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 436         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 437         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 438         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 439         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 440         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 441         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 442         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 443         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 444         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 445         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 446         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 447 };
 448
 449 struct display_info_t {
 450         int     bus;
 451         int     addr;
 452         int     pixfmt;
 453         int     (*detect)(struct display_info_t const *dev);
 454         void    (*enable)(struct display_info_t const *dev);
 455         struct  fb_videomode mode;
 456 };
 457
 458
 459 static int detect_hdmi(struct display_info_t const *dev)
 460 {
 461         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 462         return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
 463 }
 464
 465 static void enable_hdmi(struct display_info_t const *dev)
 466 {
 467         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 468         u8 reg;
 469         printf("%s: setup HDMI monitor\n", __func__);
 470         reg = readb(&hdmi->phy_conf0);
 471         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 472         writeb(reg, &hdmi->phy_conf0);
 473
 474         udelay(3000);
 475         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 476         writeb(reg, &hdmi->phy_conf0);
 477         udelay(3000);
 478         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 479         writeb(reg, &hdmi->phy_conf0);
 480         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 481 }
 482
 483 static int detect_i2c(struct display_info_t const *dev)
 484 {
 485         return ((0 == i2c_set_bus_num(dev->bus))
 486                 &&
 487                 (0 == i2c_probe(dev->addr)));
 488 }
 489
 490 static void enable_lvds(struct display_info_t const *dev)
 491 {
 492         struct iomuxc *iomux = (struct iomuxc *)
 493                                 IOMUXC_BASE_ADDR;
 494         u32 reg = readl(&iomux->gpr[2]);
 495         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 496         writel(reg, &iomux->gpr[2]);
 497         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 498 }
 499
 500 static void enable_rgb(struct display_info_t const *dev)
 501 {
 502         imx_iomux_v3_setup_multiple_pads(
 503                 rgb_pads,
 504                  ARRAY_SIZE(rgb_pads));
 505         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 506 }
 507
 508 static struct display_info_t const displays[] = {{
 509         .bus    = -1,
 510         .addr   = 0,
 511         .pixfmt = IPU_PIX_FMT_RGB24,
 512         .detect = detect_hdmi,
 513         .enable = enable_hdmi,
 514         .mode   = {
 515                 .name           = "HDMI",
 516                 .refresh        = 60,
 517                 .xres           = 1024,
 518                 .yres           = 768,
 519                 .pixclock       = 15385,
 520                 .left_margin    = 220,
 521                 .right_margin   = 40,
 522                 .upper_margin   = 21,
 523                 .lower_margin   = 7,
 524                 .hsync_len      = 60,
 525                 .vsync_len      = 10,
 526                 .sync           = FB_SYNC_EXT,
 527                 .vmode          = FB_VMODE_NONINTERLACED
 528 } }, {
 529         .bus    = 2,
 530         .addr   = 0x4,
 531         .pixfmt = IPU_PIX_FMT_LVDS666,
 532         .detect = detect_i2c,
 533         .enable = enable_lvds,
 534         .mode   = {
 535                 .name           = "Hannstar-XGA",
 536                 .refresh        = 60,
 537                 .xres           = 1024,
 538                 .yres           = 768,
 539                 .pixclock       = 15385,
 540                 .left_margin    = 220,
 541                 .right_margin   = 40,
 542                 .upper_margin   = 21,
 543                 .lower_margin   = 7,
 544                 .hsync_len      = 60,
 545                 .vsync_len      = 10,
 546                 .sync           = FB_SYNC_EXT,
 547                 .vmode          = FB_VMODE_NONINTERLACED
 548 } }, {
 549         .bus    = 2,
 550         .addr   = 0x38,
 551         .pixfmt = IPU_PIX_FMT_LVDS666,
 552         .detect = detect_i2c,
 553         .enable = enable_lvds,
 554         .mode   = {
 555                 .name           = "wsvga-lvds",
 556                 .refresh        = 60,
 557                 .xres           = 1024,
 558                 .yres           = 600,
 559                 .pixclock       = 15385,
 560                 .left_margin    = 220,
 561                 .right_margin   = 40,
 562                 .upper_margin   = 21,
 563                 .lower_margin   = 7,
 564                 .hsync_len      = 60,
 565                 .vsync_len      = 10,
 566                 .sync           = FB_SYNC_EXT,
 567                 .vmode          = FB_VMODE_NONINTERLACED
 568 } }, {
 569         .bus    = 2,
 570         .addr   = 0x48,
 571         .pixfmt = IPU_PIX_FMT_RGB666,
 572         .detect = detect_i2c,
 573         .enable = enable_rgb,
 574         .mode   = {
 575                 .name           = "wvga-rgb",
 576                 .refresh        = 57,
 577                 .xres           = 800,
 578                 .yres           = 480,
 579                 .pixclock       = 37037,
 580                 .left_margin    = 40,
 581                 .right_margin   = 60,
 582                 .upper_margin   = 10,
 583                 .lower_margin   = 10,
 584                 .hsync_len      = 20,
 585                 .vsync_len      = 10,
 586                 .sync           = 0,
 587                 .vmode          = FB_VMODE_NONINTERLACED
 588 } } };
 589
 590 int board_video_skip(void)
 591 {
 592         int i;
 593         int ret;
 594         char const *panel = getenv("panel");
 595         if (!panel) {
 596                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 597                         struct display_info_t const *dev = displays+i;
 598                         if (dev->detect(dev)) {
 599                                 panel = dev->mode.name;
 600                                 printf("auto-detected panel %s\n", panel);
 601                                 break;
 602                         }
 603                 }
 604                 if (!panel) {
 605                         panel = displays[0].mode.name;
 606                         printf("No panel detected: default to %s\n", panel);
 607                 }
 608         } else {
 609                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 610                         if (!strcmp(panel, displays[i].mode.name))
 611                                 break;
 612                 }
 613         }
 614         if (i < ARRAY_SIZE(displays)) {
 615                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 616                                     displays[i].pixfmt);
 617                 if (!ret) {
 618                         displays[i].enable(displays+i);
 619                         printf("Display: %s (%ux%u)\n",
 620                                displays[i].mode.name,
 621                                displays[i].mode.xres,
 622                                displays[i].mode.yres);
 623                 } else
 624                         printf("LCD %s cannot be configured: %d\n",
 625                                displays[i].mode.name, ret);
 626         } else {
 627                 printf("unsupported panel %s\n", panel);
 628                 ret = -EINVAL;
 629         }
 630         return (0 != ret);
 631 }
 632
 633 static void setup_display(void)
 634 {
 635         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 636         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 637         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 638         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 639
 640         int reg;
 641
 642         /* Turn on LDB0,IPU,IPU DI0 clocks */
 643         reg = __raw_readl(&mxc_ccm->CCGR3);
 644         reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
 645                 |MXC_CCM_CCGR3_LDB_DI0_MASK;
 646         writel(reg, &mxc_ccm->CCGR3);
 647
 648         /* Turn on HDMI PHY clock */
 649         reg = __raw_readl(&mxc_ccm->CCGR2);
 650         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
 651                |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 652         writel(reg, &mxc_ccm->CCGR2);
 653
 654         /* clear HDMI PHY reset */
 655         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 656
 657         /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 658         writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 659         writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
 660
 661         /* set LDB0, LDB1 clk select to 011/011 */
 662         reg = readl(&mxc_ccm->cs2cdr);
 663         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 664                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 665         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 666               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 667         writel(reg, &mxc_ccm->cs2cdr);
 668
 669         reg = readl(&mxc_ccm->cscmr2);
 670         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 671         writel(reg, &mxc_ccm->cscmr2);
 672
 673         reg = readl(&mxc_ccm->chsccdr);
 674         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
 675                 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
 676                 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 677         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 678                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 679               |(CHSCCDR_PODF_DIVIDE_BY_3
 680                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 681               |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 682                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 683         writel(reg, &mxc_ccm->chsccdr);
 684
 685         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 686              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 687              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 688              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 689              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 690              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 691              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 692              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 693              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 694         writel(reg, &iomux->gpr[2]);
 695
 696         reg = readl(&iomux->gpr[3]);
 697         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 698             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 699                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 700         writel(reg, &iomux->gpr[3]);
 701
 702         /* backlights off until needed */
 703         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 704                                          ARRAY_SIZE(backlight_pads));
 705         gpio_direction_input(LVDS_BACKLIGHT_GP);
 706         gpio_direction_input(RGB_BACKLIGHT_GP);
 707 }
 708 #endif
 709
 710 int board_early_init_f(void)
 711 {
 712         setup_iomux_uart();
 713         setup_buttons();
 714
 715 #if defined(CONFIG_VIDEO_IPUV3)
 716         setup_display();
 717 #endif
 718         return 0;
 719 }
 720
 721 /*
 722  * Do not overwrite the console
 723  * Use always serial for U-Boot console
 724  */
 725 int overwrite_console(void)
 726 {
 727         return 1;
 728 }
 729
 730 int board_init(void)
 731 {
 732         /* address of boot parameters */
 733         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 734
 735 #ifdef CONFIG_MXC_SPI
 736         setup_spi();
 737 #endif
 738         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 739         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 740         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 741
 742 #ifdef CONFIG_CMD_SATA
 743         setup_sata();
 744 #endif
 745
 746         return 0;
 747 }
 748
 749 int checkboard(void)
 750 {
 751         puts("Board: MX6Q-Sabre Lite\n");
 752
 753         return 0;
 754 }
 755
 756 struct button_key {
 757         char const      *name;
 758         unsigned        gpnum;
 759         char            ident;
 760 };
 761
 762 static struct button_key const buttons[] = {
 763         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 764         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 765         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 766         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 767         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 768         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 769 };
 770
 771 /*
 772  * generate a null-terminated string containing the buttons pressed
 773  * returns number of keys pressed
 774  */
 775 static int read_keys(char *buf)
 776 {
 777         int i, numpressed = 0;
 778         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 779                 if (!gpio_get_value(buttons[i].gpnum))
 780                         buf[numpressed++] = buttons[i].ident;
 781         }
 782         buf[numpressed] = '\0';
 783         return numpressed;
 784 }
 785
 786 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 787 {
 788         char envvalue[ARRAY_SIZE(buttons)+1];
 789         int numpressed = read_keys(envvalue);
 790         setenv("keybd", envvalue);
 791         return numpressed == 0;
 792 }
 793
 794 U_BOOT_CMD(
 795         kbd, 1, 1, do_kbd,
 796         "Tests for keypresses, sets 'keybd' environment variable",
 797         "Returns 0 (true) to shell if key is pressed."
 798 );
 799
 800 #ifdef CONFIG_PREBOOT
 801 static char const kbd_magic_prefix[] = "key_magic";
 802 static char const kbd_command_prefix[] = "key_cmd";
 803
 804 static void preboot_keys(void)
 805 {
 806         int numpressed;
 807         char keypress[ARRAY_SIZE(buttons)+1];
 808         numpressed = read_keys(keypress);
 809         if (numpressed) {
 810                 char *kbd_magic_keys = getenv("magic_keys");
 811                 char *suffix;
 812                 /*
 813                  * loop over all magic keys
 814                  */
 815                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 816                         char *keys;
 817                         char magic[sizeof(kbd_magic_prefix) + 1];
 818                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 819                         keys = getenv(magic);
 820                         if (keys) {
 821                                 if (!strcmp(keys, keypress))
 822                                         break;
 823                         }
 824                 }
 825                 if (*suffix) {
 826                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 827                         char *cmd;
 828                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 829                         cmd = getenv(cmd_name);
 830                         if (cmd) {
 831                                 setenv("preboot", cmd);
 832                                 return;
 833                         }
 834                 }
 835         }
 836 }
 837 #endif
 838
 839 #ifdef CONFIG_CMD_BMODE
 840 static const struct boot_mode board_boot_modes[] = {
 841         /* 4 bit bus width */
 842         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 843         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 844         {NULL,          0},
 845 };
 846 #endif
 847
 848 int misc_init_r(void)
 849 {
 850 #ifdef CONFIG_PREBOOT
 851         preboot_keys();
 852 #endif
 853
 854 #ifdef CONFIG_CMD_BMODE
 855         add_board_boot_modes(board_boot_modes);
 856 #endif
 857         return 0;
 858 }