2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Authors: Timur Tabi <timur@freescale.com>
5 * FSL DIU Framebuffer driver
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
16 #include <stdio_dev.h>
18 #include "../common/ngpixis.h"
19 #include <fsl_diu_fb.h>
21 #define PX_BRDCFG0_ELBC_DIU 0x02
23 #define PX_BRDCFG1_DVIEN 0x80
24 #define PX_BRDCFG1_DFPEN 0x40
25 #define PX_BRDCFG1_BACKLIGHT 0x20
30 * Note that we need to byte-swap the value before it's written to the AD
31 * register. So even though the registers don't look like they're in the same
32 * bit positions as they are on the MPC8610, the same value is written to the
33 * AD register on the MPC8610 and on the P1022.
35 #define AD_BYTE_F 0x10000000
36 #define AD_ALPHA_C_SHIFT 25
37 #define AD_BLUE_C_SHIFT 23
38 #define AD_GREEN_C_SHIFT 21
39 #define AD_RED_C_SHIFT 19
40 #define AD_PIXEL_S_SHIFT 16
41 #define AD_COMP_3_SHIFT 12
42 #define AD_COMP_2_SHIFT 8
43 #define AD_COMP_1_SHIFT 4
44 #define AD_COMP_0_SHIFT 0
46 void diu_set_pixel_clock(unsigned int pixclock)
48 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 unsigned long speed_ccb, temp;
52 speed_ccb = get_bus_freq(0);
53 temp = 1000000000 / pixclock;
55 pixval = speed_ccb / temp;
56 debug("DIU pixval = %lu\n", pixval);
58 /* Modify PXCLK in GUTS CLKDVDR */
59 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
60 out_be32(&gur->clkdvdr, temp); /* turn off clock */
61 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
64 int platform_diu_init(unsigned int *xres, unsigned int *yres)
66 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
71 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
72 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
73 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
74 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
75 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
77 temp = in_8(&pixis->brdcfg1);
79 monitor_port = getenv("monitor");
80 if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
83 /* Enable the DFP port, disable the DVI and the backlight */
84 temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT);
85 temp |= PX_BRDCFG1_DFPEN;
89 /* Enable the DVI port, disable the DFP and the backlight */
90 temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
91 temp |= PX_BRDCFG1_DVIEN;
94 out_8(&pixis->brdcfg1, temp);
97 * Route the LAD pins to the DIU. This will disable access to the eLBC,
98 * which means we won't be able to read/write any NOR flash addresses!
100 out_8(&pixis->brdcfg0, in_8(&pixis->brdcfg0) | PX_BRDCFG0_ELBC_DIU);
101 /* we must do the dummy read from eLBC to sync the write as above */
102 in_8(&pixis->brdcfg0);
104 /* Setting PMUXCR to switch to DVI from ELBC */
105 /* Set pmuxcr to allow both i2c1 and i2c2 */
106 clrsetbits_be32(&gur->pmuxcr, 0xc0000000, 0x40000000);
107 in_be32(&gur->pmuxcr);
109 return fsl_diu_init(*xres, pixel_format, 0);