2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
36 #include <fdt_support.h>
38 #include <asm/fsl_law.h>
42 #include "../common/ngpixis.h"
43 #include "../common/sgmii_riser.h"
45 DECLARE_GLOBAL_DATA_PTR;
47 phys_size_t fixed_sdram(void);
53 puts("Board: P2020DS ");
54 #ifdef CONFIG_PHYS_64BIT
55 puts("(36-bit addrmap) ");
58 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
59 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
61 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
62 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
65 /* The lower two bits are the actual vbank number */
66 printf("vBank: %d\n", sw & 3);
73 phys_size_t initdram(int board_type)
75 phys_size_t dram_size = 0;
77 puts("Initializing....");
80 dram_size = fsl_ddr_sdram();
82 dram_size = fixed_sdram();
84 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
86 LAW_TRGT_IF_DDR) < 0) {
87 printf("ERROR setting Local Access Windows for DDR\n");
91 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
92 dram_size *= 0x100000;
98 #if !defined(CONFIG_DDR_SPD)
100 * Fixed sdram init -- doesn't use serial presence detect.
103 phys_size_t fixed_sdram(void)
105 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
108 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
109 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
110 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
111 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
112 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
113 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
114 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
115 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
116 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
117 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
118 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
119 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
120 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
121 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
122 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
124 if (!strcmp("performance", getenv("perf_mode"))) {
125 /* Performance Mode Values */
127 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
128 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
129 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
130 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
131 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
137 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
139 /* Stable Mode Values */
141 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
142 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
143 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
144 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
145 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
147 /* ECC will be assumed in stable mode */
148 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
149 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
150 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
156 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
159 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
161 debug("DDR - 1st controller: memory initializing\n");
163 * Poll until memory is initialized.
164 * 512 Meg at 400 might hit this 200 times or so.
166 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
168 debug("DDR: memory initialized\n\n");
173 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
179 static struct pci_controller pcie1_hose;
183 static struct pci_controller pcie2_hose;
187 static struct pci_controller pcie3_hose;
191 void pci_init_board(void)
193 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
194 struct fsl_pci_info pci_info[3];
195 u32 devdisr, pordevsr, io_sel;
196 int first_free_busno = 0;
199 int pcie_ep, pcie_configured;
201 devdisr = in_be32(&gur->devdisr);
202 pordevsr = in_be32(&gur->pordevsr);
203 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
205 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
209 pcie_configured = is_serdes_configured(PCIE2);
211 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
212 SET_STD_PCIE_INFO(pci_info[num], 2);
213 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
214 printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
215 pcie_ep ? "Endpoint" : "Root Complex",
217 first_free_busno = fsl_pci_init_port(&pci_info[num++],
218 &pcie2_hose, first_free_busno);
221 * The workaround doesn't work on p2020 because the location
222 * we try and read isn't valid on p2020, fix this later
226 * Activate ULI1575 legacy chip by performing a fake
227 * memory access. Needed to make ULI RTC work.
228 * Device 1d has the first on-board memory BAR.
231 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
232 PCI_BASE_ADDRESS_1, &temp32);
233 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
234 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
236 debug(" uli1575 read to %p\n", p);
241 printf("PCIE2: disabled\n");
245 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
249 pcie_configured = is_serdes_configured(PCIE3);
251 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
252 SET_STD_PCIE_INFO(pci_info[num], 3);
253 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
254 printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
255 pcie_ep ? "Endpoint" : "Root Complex",
257 first_free_busno = fsl_pci_init_port(&pci_info[num++],
258 &pcie3_hose, first_free_busno);
260 printf("PCIE3: disabled\n");
264 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
268 pcie_configured = is_serdes_configured(PCIE1);
270 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
271 SET_STD_PCIE_INFO(pci_info[num], 1);
272 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
273 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
274 pcie_ep ? "Endpoint" : "Root Complex",
276 first_free_busno = fsl_pci_init_port(&pci_info[num++],
277 &pcie1_hose, first_free_busno);
279 printf("PCIE1: disabled\n");
283 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
288 int board_early_init_r(void)
290 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
291 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
294 * Remap Boot flash + PROMJET region to caching-inhibited
295 * so that flash can be erased properly.
298 /* Flush d-cache and invalidate i-cache of any FLASH data */
302 /* invalidate existing TLB entry for flash + promjet */
303 disable_tlb(flash_esel);
305 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
306 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
307 0, flash_esel, BOOKE_PAGESZ_256M, 1);
312 #ifdef CONFIG_TSEC_ENET
313 int board_eth_init(bd_t *bis)
315 struct tsec_info_struct tsec_info[4];
319 SET_STD_TSEC_INFO(tsec_info[num], 1);
323 SET_STD_TSEC_INFO(tsec_info[num], 2);
324 if (is_serdes_configured(SGMII_TSEC2)) {
325 puts("eTSEC2 is in sgmii mode.\n");
326 tsec_info[num].flags |= TSEC_SGMII;
331 SET_STD_TSEC_INFO(tsec_info[num], 3);
332 if (is_serdes_configured(SGMII_TSEC3)) {
333 puts("eTSEC3 is in sgmii mode.\n");
334 tsec_info[num].flags |= TSEC_SGMII;
340 printf("No TSECs initialized\n");
345 #ifdef CONFIG_FSL_SGMII_RISER
346 fsl_sgmii_riser_init(tsec_info, num);
349 tsec_eth_init(bis, tsec_info, num);
351 return pci_eth_init(bis);
355 #if defined(CONFIG_OF_BOARD_SETUP)
356 void ft_board_setup(void *blob, bd_t *bd)
361 ft_cpu_setup(blob, bd);
363 base = getenv_bootm_low();
364 size = getenv_bootm_size();
366 fdt_fixup_memory(blob, (u64)base, (u64)size);
370 #ifdef CONFIG_FSL_SGMII_RISER
371 fsl_sgmii_riser_fdt_fixup(blob);
377 void board_lmb_reserve(struct lmb *lmb)
379 cpu_mp_lmb_reserve(lmb);