board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <asm/fsl_serdes.h>
  34 #include <miiphy.h>
  35 #include <libfdt.h>
  36 #include <fdt_support.h>
  37 #include <tsec.h>
  38 #include <asm/fsl_law.h>
  39 #include <netdev.h>
  40
  41 #include "../common/ngpixis.h"
  42 #include "../common/sgmii_riser.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 int board_early_init_f(void)
  47 {
  48 #ifdef CONFIG_MMC
  49         ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  50
  51         setbits_be32(&gur->pmuxcr,
  52                          (MPC85xx_PMUXCR_SDHC_CD |
  53                          MPC85xx_PMUXCR_SDHC_WP));
  54 #endif
  55
  56         return 0;
  57 }
  58
  59 int checkboard(void)
  60 {
  61         u8 sw;
  62
  63         puts("Board: P2020DS ");
  64 #ifdef CONFIG_PHYS_64BIT
  65         puts("(36-bit addrmap) ");
  66 #endif
  67
  68         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  69                 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  70
  71         sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  72         sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  73
  74         if (sw < 0x8)
  75                 /* The lower two bits are the actual vbank number */
  76                 printf("vBank: %d\n", sw & 3);
  77         else
  78                 puts("Promjet\n");
  79
  80         return 0;
  81 }
  82
  83 #if !defined(CONFIG_DDR_SPD)
  84 /*
  85  * Fixed sdram init -- doesn't use serial presence detect.
  86  */
  87
  88 phys_size_t fixed_sdram(void)
  89 {
  90         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  91         uint d_init;
  92
  93         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  94         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  95         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  96         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  97         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  98         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
  99         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 100         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 101         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 102         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 103         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 104         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 105         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 106         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 107         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 108
 109         if (!strcmp("performance", getenv("perf_mode"))) {
 110                 /* Performance Mode Values */
 111
 112                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 113                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 114                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 115                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 116                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 117
 118                 asm("sync;isync");
 119
 120                 udelay(500);
 121
 122                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 123         } else {
 124                 /* Stable Mode Values */
 125
 126                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 127                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 128                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 129                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 130                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 131
 132                 /* ECC will be assumed in stable mode */
 133                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 134                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 135                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 136
 137                 asm("sync;isync");
 138
 139                 udelay(500);
 140
 141                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 142         }
 143
 144 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 145         d_init = 1;
 146         debug("DDR - 1st controller: memory initializing\n");
 147         /*
 148          * Poll until memory is initialized.
 149          * 512 Meg at 400 might hit this 200 times or so.
 150          */
 151         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 152                 udelay(1000);
 153         debug("DDR: memory initialized\n\n");
 154         asm("sync; isync");
 155         udelay(500);
 156 #endif
 157
 158         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 159                          CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
 160                          LAW_TRGT_IF_DDR) < 0) {
 161                 printf("ERROR setting Local Access Windows for DDR\n");
 162                 return 0;
 163         };
 164
 165         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 166 }
 167
 168 #endif
 169
 170 #ifdef CONFIG_PCI
 171 void pci_init_board(void)
 172 {
 173         fsl_pcie_init_board(0);
 174 }
 175 #endif
 176
 177 int board_early_init_r(void)
 178 {
 179         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 180         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 181
 182         /*
 183          * Remap Boot flash + PROMJET region to caching-inhibited
 184          * so that flash can be erased properly.
 185          */
 186
 187         /* Flush d-cache and invalidate i-cache of any FLASH data */
 188         flush_dcache();
 189         invalidate_icache();
 190
 191         /* invalidate existing TLB entry for flash + promjet */
 192         disable_tlb(flash_esel);
 193
 194         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 195                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 196                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 197
 198         return 0;
 199 }
 200
 201 #ifdef CONFIG_TSEC_ENET
 202 int board_eth_init(bd_t *bis)
 203 {
 204         struct tsec_info_struct tsec_info[4];
 205         int num = 0;
 206
 207 #ifdef CONFIG_TSEC1
 208         SET_STD_TSEC_INFO(tsec_info[num], 1);
 209         num++;
 210 #endif
 211 #ifdef CONFIG_TSEC2
 212         SET_STD_TSEC_INFO(tsec_info[num], 2);
 213         if (is_serdes_configured(SGMII_TSEC2)) {
 214                 puts("eTSEC2 is in sgmii mode.\n");
 215                 tsec_info[num].flags |= TSEC_SGMII;
 216         }
 217         num++;
 218 #endif
 219 #ifdef CONFIG_TSEC3
 220         SET_STD_TSEC_INFO(tsec_info[num], 3);
 221         if (is_serdes_configured(SGMII_TSEC3)) {
 222                 puts("eTSEC3 is in sgmii mode.\n");
 223                 tsec_info[num].flags |= TSEC_SGMII;
 224 }
 225         num++;
 226 #endif
 227
 228         if (!num) {
 229                 printf("No TSECs initialized\n");
 230
 231                 return 0;
 232         }
 233
 234 #ifdef CONFIG_FSL_SGMII_RISER
 235         fsl_sgmii_riser_init(tsec_info, num);
 236 #endif
 237
 238         tsec_eth_init(bis, tsec_info, num);
 239
 240         return pci_eth_init(bis);
 241 }
 242 #endif
 243
 244 #if defined(CONFIG_OF_BOARD_SETUP)
 245 void ft_board_setup(void *blob, bd_t *bd)
 246 {
 247         phys_addr_t base;
 248         phys_size_t size;
 249
 250         ft_cpu_setup(blob, bd);
 251
 252         base = getenv_bootm_low();
 253         size = getenv_bootm_size();
 254
 255         fdt_fixup_memory(blob, (u64)base, (u64)size);
 256
 257         FT_FSL_PCI_SETUP;
 258
 259 #ifdef CONFIG_FSL_SGMII_RISER
 260         fsl_sgmii_riser_fdt_fixup(blob);
 261 #endif
 262 }
 263 #endif