board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/video.h>
  24 #include <jffs2/load_kernel.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <linux/ctype.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <mmc.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "ventana_eeprom.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO's common to all baseboards */
  47 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  48 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  49 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  50 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  51 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  52
  53 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  54         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  55         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  59         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  63         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  64
  65 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  66         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  67         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  68
  69 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  70         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  71         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  72
  73 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  74         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  75         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  76
  77 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  78         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  79         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  80
  81 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  82
  83
  84 /*
  85  * EEPROM board info struct populated by read_eeprom so that we only have to
  86  * read it once.
  87  */
  88 struct ventana_board_info ventana_info;
  89
  90 int board_type;
  91
  92 /* UART1: Function varies per baseboard */
  93 iomux_v3_cfg_t const uart1_pads[] = {
  94         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  95         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  96 };
  97
  98 /* UART2: Serial Console */
  99 iomux_v3_cfg_t const uart2_pads[] = {
 100         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 101         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 102 };
 103
 104 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 105
 106 /* I2C1: GSC */
 107 struct i2c_pads_info mx6q_i2c_pad_info0 = {
 108         .scl = {
 109                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 110                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 111                 .gp = IMX_GPIO_NR(3, 21)
 112         },
 113         .sda = {
 114                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 115                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 116                 .gp = IMX_GPIO_NR(3, 28)
 117         }
 118 };
 119 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 120         .scl = {
 121                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 122                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 123                 .gp = IMX_GPIO_NR(3, 21)
 124         },
 125         .sda = {
 126                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 127                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 128                 .gp = IMX_GPIO_NR(3, 28)
 129         }
 130 };
 131
 132 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 133 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 134         .scl = {
 135                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 136                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 137                 .gp = IMX_GPIO_NR(4, 12)
 138         },
 139         .sda = {
 140                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 141                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 142                 .gp = IMX_GPIO_NR(4, 13)
 143         }
 144 };
 145 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 146         .scl = {
 147                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 148                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 149                 .gp = IMX_GPIO_NR(4, 12)
 150         },
 151         .sda = {
 152                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 153                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 154                 .gp = IMX_GPIO_NR(4, 13)
 155         }
 156 };
 157
 158 /* I2C3: Misc/Expansion */
 159 struct i2c_pads_info mx6q_i2c_pad_info2 = {
 160         .scl = {
 161                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 162                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 163                 .gp = IMX_GPIO_NR(1, 3)
 164         },
 165         .sda = {
 166                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 167                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 168                 .gp = IMX_GPIO_NR(1, 6)
 169         }
 170 };
 171 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 172         .scl = {
 173                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 174                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 175                 .gp = IMX_GPIO_NR(1, 3)
 176         },
 177         .sda = {
 178                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 179                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 180                 .gp = IMX_GPIO_NR(1, 6)
 181         }
 182 };
 183
 184 /* MMC */
 185 iomux_v3_cfg_t const usdhc3_pads[] = {
 186         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 187         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 188         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 190         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         /* CD */
 193         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 194 };
 195
 196 /* ENET */
 197 iomux_v3_cfg_t const enet_pads[] = {
 198         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 199         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 200         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 206                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 208                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 210         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 212         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 215                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         /* PHY nRST */
 217         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 218 };
 219
 220 /* NAND */
 221 iomux_v3_cfg_t const nfc_pads[] = {
 222         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 223         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 224         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237 };
 238
 239 #ifdef CONFIG_CMD_NAND
 240 static void setup_gpmi_nand(void)
 241 {
 242         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 243
 244         /* config gpmi nand iomux */
 245         SETUP_IOMUX_PADS(nfc_pads);
 246
 247         /* config gpmi and bch clock to 100 MHz */
 248         clrsetbits_le32(&mxc_ccm->cs2cdr,
 249                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 250                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 251                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 252                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 253                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 254                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 255
 256         /* enable gpmi and bch clock gating */
 257         setbits_le32(&mxc_ccm->CCGR4,
 258                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 259                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 260                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 261                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 262                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 263
 264         /* enable apbh clock gating */
 265         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 266 }
 267 #endif
 268
 269 static void setup_iomux_enet(void)
 270 {
 271         SETUP_IOMUX_PADS(enet_pads);
 272
 273         /* toggle PHY_RST# */
 274         gpio_direction_output(GP_PHY_RST, 0);
 275         mdelay(2);
 276         gpio_set_value(GP_PHY_RST, 1);
 277 }
 278
 279 static void setup_iomux_uart(void)
 280 {
 281         SETUP_IOMUX_PADS(uart1_pads);
 282         SETUP_IOMUX_PADS(uart2_pads);
 283 }
 284
 285 #ifdef CONFIG_USB_EHCI_MX6
 286 iomux_v3_cfg_t const usb_pads[] = {
 287         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 288         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 289         /* OTG PWR */
 290         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 291 };
 292
 293 int board_ehci_hcd_init(int port)
 294 {
 295         struct ventana_board_info *info = &ventana_info;
 296
 297         SETUP_IOMUX_PADS(usb_pads);
 298
 299         /* Reset USB HUB (present on GW54xx/GW53xx) */
 300         switch (info->model[3]) {
 301         case '3': /* GW53xx */
 302         case '5': /* GW552x */
 303                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 304                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 305                 mdelay(2);
 306                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 307                 break;
 308         case '4': /* GW54xx */
 309                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 310                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 311                 mdelay(2);
 312                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 313                 break;
 314         }
 315
 316         return 0;
 317 }
 318
 319 int board_ehci_power(int port, int on)
 320 {
 321         if (port)
 322                 return 0;
 323         gpio_set_value(GP_USB_OTG_PWR, on);
 324         return 0;
 325 }
 326 #endif /* CONFIG_USB_EHCI_MX6 */
 327
 328 #ifdef CONFIG_FSL_ESDHC
 329 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 330
 331 int board_mmc_getcd(struct mmc *mmc)
 332 {
 333         /* Card Detect */
 334         gpio_direction_input(GP_SD3_CD);
 335         return !gpio_get_value(GP_SD3_CD);
 336 }
 337
 338 int board_mmc_init(bd_t *bis)
 339 {
 340         /* Only one USDHC controller on Ventana */
 341         SETUP_IOMUX_PADS(usdhc3_pads);
 342         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 343         usdhc_cfg.max_bus_width = 4;
 344
 345         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 346 }
 347 #endif /* CONFIG_FSL_ESDHC */
 348
 349 #ifdef CONFIG_MXC_SPI
 350 iomux_v3_cfg_t const ecspi1_pads[] = {
 351         /* SS1 */
 352         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 353         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 354         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 355         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 356 };
 357
 358 static void setup_spi(void)
 359 {
 360         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 361         SETUP_IOMUX_PADS(ecspi1_pads);
 362 }
 363 #endif
 364
 365 /* configure eth0 PHY board-specific LED behavior */
 366 int board_phy_config(struct phy_device *phydev)
 367 {
 368         unsigned short val;
 369
 370         /* Marvel 88E1510 */
 371         if (phydev->phy_id == 0x1410dd1) {
 372                 /*
 373                  * Page 3, Register 16: LED[2:0] Function Control Register
 374                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 375                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 376                  */
 377                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 378                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 379                 val &= 0xff00;
 380                 val |= 0x0017;
 381                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 382                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 383         }
 384
 385         if (phydev->drv->config)
 386                 phydev->drv->config(phydev);
 387
 388         return 0;
 389 }
 390
 391 int board_eth_init(bd_t *bis)
 392 {
 393         setup_iomux_enet();
 394
 395 #ifdef CONFIG_FEC_MXC
 396         if (board_type != GW552x)
 397                 cpu_eth_init(bis);
 398 #endif
 399
 400 #ifdef CONFIG_CI_UDC
 401         /* For otg ethernet*/
 402         usb_eth_initialize(bis);
 403 #endif
 404
 405         return 0;
 406 }
 407
 408 #if defined(CONFIG_VIDEO_IPUV3)
 409
 410 static void enable_hdmi(struct display_info_t const *dev)
 411 {
 412         imx_enable_hdmi_phy();
 413 }
 414
 415 static int detect_i2c(struct display_info_t const *dev)
 416 {
 417         return i2c_set_bus_num(dev->bus) == 0 &&
 418                 i2c_probe(dev->addr) == 0;
 419 }
 420
 421 static void enable_lvds(struct display_info_t const *dev)
 422 {
 423         struct iomuxc *iomux = (struct iomuxc *)
 424                                 IOMUXC_BASE_ADDR;
 425
 426         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 427         u32 reg = readl(&iomux->gpr[2]);
 428         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 429         writel(reg, &iomux->gpr[2]);
 430
 431         /* Enable Backlight */
 432         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 433         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 434 }
 435
 436 struct display_info_t const displays[] = {{
 437         /* HDMI Output */
 438         .bus    = -1,
 439         .addr   = 0,
 440         .pixfmt = IPU_PIX_FMT_RGB24,
 441         .detect = detect_hdmi,
 442         .enable = enable_hdmi,
 443         .mode   = {
 444                 .name           = "HDMI",
 445                 .refresh        = 60,
 446                 .xres           = 1024,
 447                 .yres           = 768,
 448                 .pixclock       = 15385,
 449                 .left_margin    = 220,
 450                 .right_margin   = 40,
 451                 .upper_margin   = 21,
 452                 .lower_margin   = 7,
 453                 .hsync_len      = 60,
 454                 .vsync_len      = 10,
 455                 .sync           = FB_SYNC_EXT,
 456                 .vmode          = FB_VMODE_NONINTERLACED
 457 } }, {
 458         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 459         .bus    = 2,
 460         .addr   = 0x4,
 461         .pixfmt = IPU_PIX_FMT_LVDS666,
 462         .detect = detect_i2c,
 463         .enable = enable_lvds,
 464         .mode   = {
 465                 .name           = "Hannstar-XGA",
 466                 .refresh        = 60,
 467                 .xres           = 1024,
 468                 .yres           = 768,
 469                 .pixclock       = 15385,
 470                 .left_margin    = 220,
 471                 .right_margin   = 40,
 472                 .upper_margin   = 21,
 473                 .lower_margin   = 7,
 474                 .hsync_len      = 60,
 475                 .vsync_len      = 10,
 476                 .sync           = FB_SYNC_EXT,
 477                 .vmode          = FB_VMODE_NONINTERLACED
 478 } } };
 479 size_t display_count = ARRAY_SIZE(displays);
 480
 481 static void setup_display(void)
 482 {
 483         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 484         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 485         int reg;
 486
 487         enable_ipu_clock();
 488         imx_setup_hdmi();
 489         /* Turn on LDB0,IPU,IPU DI0 clocks */
 490         reg = __raw_readl(&mxc_ccm->CCGR3);
 491         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 492         writel(reg, &mxc_ccm->CCGR3);
 493
 494         /* set LDB0, LDB1 clk select to 011/011 */
 495         reg = readl(&mxc_ccm->cs2cdr);
 496         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 497                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 498         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 499               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 500         writel(reg, &mxc_ccm->cs2cdr);
 501
 502         reg = readl(&mxc_ccm->cscmr2);
 503         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 504         writel(reg, &mxc_ccm->cscmr2);
 505
 506         reg = readl(&mxc_ccm->chsccdr);
 507         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 508                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 509         writel(reg, &mxc_ccm->chsccdr);
 510
 511         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 512              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 513              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 514              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 515              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 516              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 517              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 518              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 519              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 520         writel(reg, &iomux->gpr[2]);
 521
 522         reg = readl(&iomux->gpr[3]);
 523         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 524             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 525                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 526         writel(reg, &iomux->gpr[3]);
 527
 528         /* Backlight CABEN on LVDS connector */
 529         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 530         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 531 }
 532 #endif /* CONFIG_VIDEO_IPUV3 */
 533
 534 /*
 535  * Baseboard specific GPIO
 536  */
 537
 538 /* common to add baseboards */
 539 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 540         /* MSATA_EN */
 541         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 542         /* RS232_EN# */
 543         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 544 };
 545
 546 /* prototype */
 547 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 548         /* PANLEDG# */
 549         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 550         /* PANLEDR# */
 551         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 552         /* LOCLED# */
 553         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 554         /* RS485_EN */
 555         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 556         /* IOEXP_PWREN# */
 557         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 558         /* IOEXP_IRQ# */
 559         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 560         /* VID_EN */
 561         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 562         /* DIOI2C_DIS# */
 563         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 564         /* PCICK_SSON */
 565         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 566         /* PCI_RST# */
 567         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 568 };
 569
 570 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 571         /* PANLEDG# */
 572         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 573         /* PANLEDR# */
 574         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 575         /* IOEXP_PWREN# */
 576         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 577         /* IOEXP_IRQ# */
 578         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 579
 580         /* GPS_SHDN */
 581         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 582         /* VID_PWR */
 583         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 584         /* PCI_RST# */
 585         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 586         /* PCIESKT_WDIS# */
 587         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 588 };
 589
 590 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 591         /* PANLEDG# */
 592         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 593         /* PANLEDR# */
 594         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 595         /* IOEXP_PWREN# */
 596         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 597         /* IOEXP_IRQ# */
 598         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 599
 600         /* MX6_LOCLED# */
 601         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 602         /* GPS_SHDN */
 603         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 604         /* USBOTG_SEL */
 605         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 606         /* VID_PWR */
 607         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 608         /* PCI_RST# */
 609         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 610         /* PCIESKT_WDIS# */
 611         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 612 };
 613
 614 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 615         /* PANLEDG# */
 616         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 617         /* PANLEDR# */
 618         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 619         /* MX6_LOCLED# */
 620         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 621         /* IOEXP_PWREN# */
 622         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 623         /* IOEXP_IRQ# */
 624         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 625         /* DIOI2C_DIS# */
 626         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 627         /* GPS_SHDN */
 628         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 629         /* VID_EN */
 630         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 631         /* PCI_RST# */
 632         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 633         /* PCIESKT_WDIS# */
 634         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 635 };
 636
 637 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 638         /* PANLEDG# */
 639         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 640         /* PANLEDR# */
 641         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 642         /* MX6_LOCLED# */
 643         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 644         /* MIPI_DIO */
 645         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 646         /* RS485_EN */
 647         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 648         /* IOEXP_PWREN# */
 649         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 650         /* IOEXP_IRQ# */
 651         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 652         /* DIOI2C_DIS# */
 653         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 654         /* PCICK_SSON */
 655         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 656         /* PCI_RST# */
 657         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 658         /* VID_EN */
 659         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 660         /* PCIESKT_WDIS# */
 661         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 662 };
 663
 664 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 665         /* PANLEDG# */
 666         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 667         /* PANLEDR# */
 668         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 669         /* MX6_LOCLED# */
 670         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 671         /* PCI_RST# */
 672         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 673         /* MX6_DIO[4:9] */
 674         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
 675         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 676         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
 677         IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
 678         IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
 679         IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
 680         /* PCIEGBE1_OFF# */
 681         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
 682         /* PCIEGBE2_OFF# */
 683         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 684         /* PCIESKT_WDIS# */
 685         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 686 };
 687
 688 /*
 689  * each baseboard has 4 user configurable Digital IO lines which can
 690  * be pinmuxed as a GPIO or in some cases a PWM
 691  */
 692 struct dio_cfg {
 693         iomux_v3_cfg_t gpio_padmux[2];
 694         unsigned gpio_param;
 695         iomux_v3_cfg_t pwm_padmux[2];
 696         unsigned pwm_param;
 697 };
 698
 699 struct ventana {
 700         /* pinmux */
 701         iomux_v3_cfg_t const *gpio_pads;
 702         int num_pads;
 703         /* DIO pinmux/val */
 704         struct dio_cfg dio_cfg[4];
 705         /* various gpios (0 if non-existent) */
 706         int leds[3];
 707         int pcie_rst;
 708         int mezz_pwren;
 709         int mezz_irq;
 710         int rs485en;
 711         int gps_shdn;
 712         int vidin_en;
 713         int dioi2c_en;
 714         int pcie_sson;
 715         int usb_sel;
 716         int wdis;
 717 };
 718
 719 struct ventana gpio_cfg[] = {
 720         /* GW5400proto */
 721         {
 722                 .gpio_pads = gw54xx_gpio_pads,
 723                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 724                 .dio_cfg = {
 725                         {
 726                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 727                                 IMX_GPIO_NR(1, 9),
 728                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 729                                 1
 730                         },
 731                         {
 732                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 733                                 IMX_GPIO_NR(1, 19),
 734                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 735                                 2
 736                         },
 737                         {
 738                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 739                                 IMX_GPIO_NR(2, 9),
 740                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 741                                 3
 742                         },
 743                         {
 744                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 745                                 IMX_GPIO_NR(2, 10),
 746                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 747                                 4
 748                         },
 749                 },
 750                 .leds = {
 751                         IMX_GPIO_NR(4, 6),
 752                         IMX_GPIO_NR(4, 10),
 753                         IMX_GPIO_NR(4, 15),
 754                 },
 755                 .pcie_rst = IMX_GPIO_NR(1, 29),
 756                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 757                 .mezz_irq = IMX_GPIO_NR(4, 9),
 758                 .rs485en = IMX_GPIO_NR(3, 24),
 759                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 760                 .pcie_sson = IMX_GPIO_NR(1, 20),
 761         },
 762
 763         /* GW51xx */
 764         {
 765                 .gpio_pads = gw51xx_gpio_pads,
 766                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 767                 .dio_cfg = {
 768                         {
 769                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 770                                 IMX_GPIO_NR(1, 16),
 771                                 { 0, 0 },
 772                                 0
 773                         },
 774                         {
 775                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 776                                 IMX_GPIO_NR(1, 19),
 777                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 778                                 2
 779                         },
 780                         {
 781                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 782                                 IMX_GPIO_NR(1, 17),
 783                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 784                                 3
 785                         },
 786                         {
 787                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 788                                 IMX_GPIO_NR(1, 18),
 789                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 790                                 4
 791                         },
 792                 },
 793                 .leds = {
 794                         IMX_GPIO_NR(4, 6),
 795                         IMX_GPIO_NR(4, 10),
 796                 },
 797                 .pcie_rst = IMX_GPIO_NR(1, 0),
 798                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 799                 .mezz_irq = IMX_GPIO_NR(2, 18),
 800                 .gps_shdn = IMX_GPIO_NR(1, 2),
 801                 .vidin_en = IMX_GPIO_NR(5, 20),
 802                 .wdis = IMX_GPIO_NR(7, 12),
 803         },
 804
 805         /* GW52xx */
 806         {
 807                 .gpio_pads = gw52xx_gpio_pads,
 808                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 809                 .dio_cfg = {
 810                         {
 811                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 812                                 IMX_GPIO_NR(1, 16),
 813                                 { 0, 0 },
 814                                 0
 815                         },
 816                         {
 817                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 818                                 IMX_GPIO_NR(1, 19),
 819                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 820                                 2
 821                         },
 822                         {
 823                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 824                                 IMX_GPIO_NR(1, 17),
 825                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 826                                 3
 827                         },
 828                         {
 829                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 830                                 IMX_GPIO_NR(1, 20),
 831                                 { 0, 0 },
 832                                 0
 833                         },
 834                 },
 835                 .leds = {
 836                         IMX_GPIO_NR(4, 6),
 837                         IMX_GPIO_NR(4, 7),
 838                         IMX_GPIO_NR(4, 15),
 839                 },
 840                 .pcie_rst = IMX_GPIO_NR(1, 29),
 841                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 842                 .mezz_irq = IMX_GPIO_NR(2, 18),
 843                 .gps_shdn = IMX_GPIO_NR(1, 27),
 844                 .vidin_en = IMX_GPIO_NR(3, 31),
 845                 .usb_sel = IMX_GPIO_NR(1, 2),
 846                 .wdis = IMX_GPIO_NR(7, 12),
 847         },
 848
 849         /* GW53xx */
 850         {
 851                 .gpio_pads = gw53xx_gpio_pads,
 852                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 853                 .dio_cfg = {
 854                         {
 855                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 856                                 IMX_GPIO_NR(1, 16),
 857                                 { 0, 0 },
 858                                 0
 859                         },
 860                         {
 861                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 862                                 IMX_GPIO_NR(1, 19),
 863                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 864                                 2
 865                         },
 866                         {
 867                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 868                                 IMX_GPIO_NR(1, 17),
 869                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 870                                 3
 871                         },
 872                         {
 873                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 874                                 IMX_GPIO_NR(1, 20),
 875                                 { 0, 0 },
 876                                 0
 877                         },
 878                 },
 879                 .leds = {
 880                         IMX_GPIO_NR(4, 6),
 881                         IMX_GPIO_NR(4, 7),
 882                         IMX_GPIO_NR(4, 15),
 883                 },
 884                 .pcie_rst = IMX_GPIO_NR(1, 29),
 885                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 886                 .mezz_irq = IMX_GPIO_NR(2, 18),
 887                 .gps_shdn = IMX_GPIO_NR(1, 27),
 888                 .vidin_en = IMX_GPIO_NR(3, 31),
 889                 .wdis = IMX_GPIO_NR(7, 12),
 890         },
 891
 892         /* GW54xx */
 893         {
 894                 .gpio_pads = gw54xx_gpio_pads,
 895                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 896                 .dio_cfg = {
 897                         {
 898                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 899                                 IMX_GPIO_NR(1, 9),
 900                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 901                                 1
 902                         },
 903                         {
 904                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 905                                 IMX_GPIO_NR(1, 19),
 906                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 907                                 2
 908                         },
 909                         {
 910                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 911                                 IMX_GPIO_NR(2, 9),
 912                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 913                                 3
 914                         },
 915                         {
 916                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 917                                 IMX_GPIO_NR(2, 10),
 918                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 919                                 4
 920                         },
 921                 },
 922                 .leds = {
 923                         IMX_GPIO_NR(4, 6),
 924                         IMX_GPIO_NR(4, 7),
 925                         IMX_GPIO_NR(4, 15),
 926                 },
 927                 .pcie_rst = IMX_GPIO_NR(1, 29),
 928                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 929                 .mezz_irq = IMX_GPIO_NR(2, 18),
 930                 .rs485en = IMX_GPIO_NR(7, 1),
 931                 .vidin_en = IMX_GPIO_NR(3, 31),
 932                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 933                 .pcie_sson = IMX_GPIO_NR(1, 20),
 934                 .wdis = IMX_GPIO_NR(5, 17),
 935         },
 936
 937         /* GW552x */
 938         {
 939                 .gpio_pads = gw552x_gpio_pads,
 940                 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
 941                 .dio_cfg = {
 942                         {
 943                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 944                                 IMX_GPIO_NR(1, 16),
 945                                 { 0, 0 },
 946                                 0
 947                         },
 948                         {
 949                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 950                                 IMX_GPIO_NR(1, 19),
 951                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 952                                 2
 953                         },
 954                         {
 955                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 956                                 IMX_GPIO_NR(1, 17),
 957                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 958                                 3
 959                         },
 960                         {
 961                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 962                                 IMX_GPIO_NR(2, 10),
 963                                 { 0, 0 },
 964                                 0
 965                         },
 966                 },
 967                 .leds = {
 968                         IMX_GPIO_NR(4, 6),
 969                         IMX_GPIO_NR(4, 7),
 970                         IMX_GPIO_NR(4, 15),
 971                 },
 972                 .pcie_rst = IMX_GPIO_NR(1, 29),
 973         },
 974 };
 975
 976 /* setup board specific PMIC */
 977 int power_init_board(void)
 978 {
 979         struct pmic *p;
 980         u32 reg;
 981
 982         /* configure PFUZE100 PMIC */
 983         if (board_type == GW54xx || board_type == GW54proto) {
 984                 power_pfuze100_init(CONFIG_I2C_PMIC);
 985                 p = pmic_get("PFUZE100");
 986                 if (p && !pmic_probe(p)) {
 987                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 988                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 989
 990                         /* Set VGEN1 to 1.5V and enable */
 991                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
 992                         reg &= ~(LDO_VOL_MASK);
 993                         reg |= (LDOA_1_50V | LDO_EN);
 994                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
 995
 996                         /* Set SWBST to 5.0V and enable */
 997                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
 998                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
 999                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1000                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1001                 }
1002         }
1003
1004         /* configure LTC3676 PMIC */
1005         else {
1006                 power_ltc3676_init(CONFIG_I2C_PMIC);
1007                 p = pmic_get("LTC3676_PMIC");
1008                 if (p && !pmic_probe(p)) {
1009                         puts("PMIC:  LTC3676\n");
1010                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
1011                         if (is_cpu_type(MXC_CPU_MX6Q)) {
1012                                 /* mask PGOOD during SW1 transition */
1013                                 reg = 0x1d | LTC3676_PGOOD_MASK;
1014                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
1015                                 /* set SW1 (VDD_SOC) to 1259mV */
1016                                 reg = 0x1d;
1017                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
1018
1019                                 /* mask PGOOD during SW3 transition */
1020                                 reg = 0x1d | LTC3676_PGOOD_MASK;
1021                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
1022                                 /*set SW3 (VDD_ARM) to 1259mV */
1023                                 reg = 0x1d;
1024                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
1025                         }
1026                 }
1027         }
1028
1029         return 0;
1030 }
1031
1032 /* setup GPIO pinmux and default configuration per baseboard */
1033 static void setup_board_gpio(int board)
1034 {
1035         struct ventana_board_info *info = &ventana_info;
1036         const char *s;
1037         char arg[10];
1038         size_t len;
1039         int i;
1040         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1041
1042         if (board >= GW_UNKNOWN)
1043                 return;
1044
1045         /* RS232_EN# */
1046         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1047
1048         /* MSATA Enable */
1049         if (is_cpu_type(MXC_CPU_MX6Q) &&
1050             test_bit(EECONFIG_SATA, info->config)) {
1051                 gpio_direction_output(GP_MSATA_SEL,
1052                                       (hwconfig("msata")) ?  1 : 0);
1053         } else {
1054                 gpio_direction_output(GP_MSATA_SEL, 0);
1055         }
1056
1057 #if !defined(CONFIG_CMD_PCI)
1058         /* assert PCI_RST# (released by OS when clock is valid) */
1059         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1060 #endif
1061
1062         /* turn off (active-high) user LED's */
1063         for (i = 0; i < 4; i++) {
1064                 if (gpio_cfg[board].leds[i])
1065                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1066         }
1067
1068         /* Expansion Mezzanine IO */
1069         if (gpio_cfg[board].mezz_pwren)
1070                 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1071         if (gpio_cfg[board].mezz_irq)
1072                 gpio_direction_input(gpio_cfg[board].mezz_irq);
1073
1074         /* RS485 Transmit Enable */
1075         if (gpio_cfg[board].rs485en)
1076                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1077
1078         /* GPS_SHDN */
1079         if (gpio_cfg[board].gps_shdn)
1080                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1081
1082         /* Analog video codec power enable */
1083         if (gpio_cfg[board].vidin_en)
1084                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1085
1086         /* DIOI2C_DIS# */
1087         if (gpio_cfg[board].dioi2c_en)
1088                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1089
1090         /* PCICK_SSON: disable spread-spectrum clock */
1091         if (gpio_cfg[board].pcie_sson)
1092                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1093
1094         /* USBOTG Select (PCISKT or FrontPanel) */
1095         if (gpio_cfg[board].usb_sel)
1096                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1097
1098         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1099         if (gpio_cfg[board].wdis)
1100                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1101
1102         /*
1103          * Configure DIO pinmux/padctl registers
1104          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1105          */
1106         for (i = 0; i < 4; i++) {
1107                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1108                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1109                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1110
1111                 sprintf(arg, "dio%d", i);
1112                 if (!hwconfig(arg))
1113                         continue;
1114                 s = hwconfig_subarg(arg, "padctrl", &len);
1115                 if (s) {
1116                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1117                                             & 0x1ffff) | MUX_MODE_SION;
1118                 }
1119                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1120                         if (!quiet) {
1121                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1122                                        (cfg->gpio_param/32)+1,
1123                                        cfg->gpio_param%32,
1124                                        cfg->gpio_param);
1125                         }
1126                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1127                                                ctrl);
1128                         gpio_direction_input(cfg->gpio_param);
1129                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1130                            cfg->pwm_padmux) {
1131                         if (!quiet)
1132                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1133                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1134                                                MUX_PAD_CTRL(ctrl));
1135                 }
1136         }
1137
1138         if (!quiet) {
1139                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1140                     (test_bit(EECONFIG_SATA, info->config))) {
1141                         printf("MSATA: %s\n", (hwconfig("msata") ?
1142                                "enabled" : "disabled"));
1143                 }
1144                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1145                        "enabled" : "disabled");
1146         }
1147 }
1148
1149 #if defined(CONFIG_CMD_PCI)
1150 int imx6_pcie_toggle_reset(void)
1151 {
1152         if (board_type < GW_UNKNOWN) {
1153                 uint pin = gpio_cfg[board_type].pcie_rst;
1154                 gpio_direction_output(pin, 0);
1155                 mdelay(50);
1156                 gpio_direction_output(pin, 1);
1157         }
1158         return 0;
1159 }
1160 #endif /* CONFIG_CMD_PCI */
1161
1162 #ifdef CONFIG_SERIAL_TAG
1163 /*
1164  * called when setting up ATAGS before booting kernel
1165  * populate serialnum from the following (in order of priority):
1166  *   serial# env var
1167  *   eeprom
1168  */
1169 void get_board_serial(struct tag_serialnr *serialnr)
1170 {
1171         char *serial = getenv("serial#");
1172
1173         if (serial) {
1174                 serialnr->high = 0;
1175                 serialnr->low = simple_strtoul(serial, NULL, 10);
1176         } else if (ventana_info.model[0]) {
1177                 serialnr->high = 0;
1178                 serialnr->low = ventana_info.serial;
1179         } else {
1180                 serialnr->high = 0;
1181                 serialnr->low = 0;
1182         }
1183 }
1184 #endif
1185
1186 /*
1187  * Board Support
1188  */
1189
1190 /* called from SPL board_init_f() */
1191 int board_early_init_f(void)
1192 {
1193         setup_iomux_uart();
1194         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1195
1196 #if defined(CONFIG_VIDEO_IPUV3)
1197         setup_display();
1198 #endif
1199         return 0;
1200 }
1201
1202 int dram_init(void)
1203 {
1204         gd->ram_size = imx_ddr_size();
1205         return 0;
1206 }
1207
1208 int board_init(void)
1209 {
1210         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1211
1212         clrsetbits_le32(&iomuxc_regs->gpr[1],
1213                         IOMUXC_GPR1_OTG_ID_MASK,
1214                         IOMUXC_GPR1_OTG_ID_GPIO1);
1215
1216         /* address of linux boot parameters */
1217         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1218
1219 #ifdef CONFIG_CMD_NAND
1220         setup_gpmi_nand();
1221 #endif
1222 #ifdef CONFIG_MXC_SPI
1223         setup_spi();
1224 #endif
1225         if (is_cpu_type(MXC_CPU_MX6Q)) {
1226                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1227                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1228                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1229         } else {
1230                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1231                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1232                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1233         }
1234
1235 #ifdef CONFIG_CMD_SATA
1236         setup_sata();
1237 #endif
1238         /* read Gateworks EEPROM into global struct (used later) */
1239         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1240
1241         /* board-specifc GPIO iomux */
1242         SETUP_IOMUX_PADS(gw_gpio_pads);
1243         if (board_type < GW_UNKNOWN) {
1244                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1245                 int count = gpio_cfg[board_type].num_pads;
1246
1247                 imx_iomux_v3_setup_multiple_pads(p, count);
1248         }
1249
1250         return 0;
1251 }
1252
1253 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1254 /*
1255  * called during late init (after relocation and after board_init())
1256  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1257  * EEPROM read.
1258  */
1259 int checkboard(void)
1260 {
1261         struct ventana_board_info *info = &ventana_info;
1262         unsigned char buf[4];
1263         const char *p;
1264         int quiet; /* Quiet or minimal output mode */
1265
1266         quiet = 0;
1267         p = getenv("quiet");
1268         if (p)
1269                 quiet = simple_strtol(p, NULL, 10);
1270         else
1271                 setenv("quiet", "0");
1272
1273         puts("\nGateworks Corporation Copyright 2014\n");
1274         if (info->model[0]) {
1275                 printf("Model: %s\n", info->model);
1276                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1277                        info->mfgdate[0], info->mfgdate[1],
1278                        info->mfgdate[2], info->mfgdate[3]);
1279                 printf("Serial:%d\n", info->serial);
1280         } else {
1281                 puts("Invalid EEPROM - board will not function fully\n");
1282         }
1283         if (quiet)
1284                 return 0;
1285
1286         /* Display GSC firmware revision/CRC/status */
1287         i2c_set_bus_num(CONFIG_I2C_GSC);
1288         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1289                 printf("GSC:   v%d", buf[0]);
1290                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1291                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1292                         printf(" 0x%02x", buf[0]); /* irq status */
1293                 }
1294                 puts("\n");
1295         }
1296         /* Display RTC */
1297         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1298                 printf("RTC:   %d\n",
1299                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1300         }
1301
1302         return 0;
1303 }
1304 #endif
1305
1306 #ifdef CONFIG_CMD_BMODE
1307 /*
1308  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1309  * see Table 8-11 and Table 5-9
1310  *  BOOT_CFG1[7] = 1 (boot from NAND)
1311  *  BOOT_CFG1[5] = 0 - raw NAND
1312  *  BOOT_CFG1[4] = 0 - default pad settings
1313  *  BOOT_CFG1[3:2] = 00 - devices = 1
1314  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1315  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1316  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1317  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1318  */
1319 static const struct boot_mode board_boot_modes[] = {
1320         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1321         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1322         { NULL, 0 },
1323 };
1324 #endif
1325
1326 /* late init */
1327 int misc_init_r(void)
1328 {
1329         struct ventana_board_info *info = &ventana_info;
1330         unsigned char reg;
1331
1332         /* set env vars based on EEPROM data */
1333         if (ventana_info.model[0]) {
1334                 char str[16], fdt[36];
1335                 char *p;
1336                 const char *cputype = "";
1337                 int i;
1338
1339                 /*
1340                  * FDT name will be prefixed with CPU type.  Three versions
1341                  * will be created each increasingly generic and bootloader
1342                  * env scripts will try loading each from most specific to
1343                  * least.
1344                  */
1345                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1346                     is_cpu_type(MXC_CPU_MX6D))
1347                         cputype = "imx6q";
1348                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1349                          is_cpu_type(MXC_CPU_MX6SOLO))
1350                         cputype = "imx6dl";
1351                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1352                         setenv("flash_layout", "large");
1353                 else
1354                         setenv("flash_layout", "normal");
1355                 memset(str, 0, sizeof(str));
1356                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1357                         str[i] = tolower(info->model[i]);
1358                 if (!getenv("model"))
1359                         setenv("model", str);
1360                 if (!getenv("fdt_file")) {
1361                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1362                         setenv("fdt_file", fdt);
1363                 }
1364                 p = strchr(str, '-');
1365                 if (p) {
1366                         *p++ = 0;
1367
1368                         setenv("model_base", str);
1369                         if (!getenv("fdt_file1")) {
1370                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1371                                 setenv("fdt_file1", fdt);
1372                         }
1373                         if (board_type != GW552x)
1374                                 str[4] = 'x';
1375                         str[5] = 'x';
1376                         str[6] = 0;
1377                         if (!getenv("fdt_file2")) {
1378                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1379                                 setenv("fdt_file2", fdt);
1380                         }
1381                 }
1382
1383                 /* initialize env from EEPROM */
1384                 if (test_bit(EECONFIG_ETH0, info->config) &&
1385                     !getenv("ethaddr")) {
1386                         eth_setenv_enetaddr("ethaddr", info->mac0);
1387                 }
1388                 if (test_bit(EECONFIG_ETH1, info->config) &&
1389                     !getenv("eth1addr")) {
1390                         eth_setenv_enetaddr("eth1addr", info->mac1);
1391                 }
1392
1393                 /* board serial-number */
1394                 sprintf(str, "%6d", info->serial);
1395                 setenv("serial#", str);
1396         }
1397
1398
1399         /* setup baseboard specific GPIO pinmux and config */
1400         setup_board_gpio(board_type);
1401
1402 #ifdef CONFIG_CMD_BMODE
1403         add_board_boot_modes(board_boot_modes);
1404 #endif
1405
1406         /*
1407          *  The Gateworks System Controller implements a boot
1408          *  watchdog (always enabled) as a workaround for IMX6 boot related
1409          *  errata such as:
1410          *    ERR005768 - no fix scheduled
1411          *    ERR006282 - fixed in silicon r1.2
1412          *    ERR007117 - fixed in silicon r1.3
1413          *    ERR007220 - fixed in silicon r1.3
1414          *    ERR007926 - no fix scheduled
1415          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1416          *
1417          * Disable the boot watchdog and display/clear the timeout flag if set
1418          */
1419         i2c_set_bus_num(CONFIG_I2C_GSC);
1420         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1421                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1422                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1423                         puts("Error: could not disable GSC Watchdog\n");
1424         } else {
1425                 puts("Error: could not disable GSC Watchdog\n");
1426         }
1427         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1428                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1429                         puts("GSC boot watchdog timeout detected\n");
1430                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1431                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1432                 }
1433         }
1434
1435         return 0;
1436 }
1437
1438 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1439
1440 /*
1441  * called prior to booting kernel or by 'fdt boardsetup' command
1442  *
1443  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1444  *  - mtd partitions based on mtdparts/mtdids env
1445  *  - system-serial (board serial num from EEPROM)
1446  *  - board (full model from EEPROM)
1447  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1448  */
1449 void ft_board_setup(void *blob, bd_t *bd)
1450 {
1451         struct ventana_board_info *info = &ventana_info;
1452         struct ventana_eeprom_config *cfg;
1453         struct node_info nodes[] = {
1454                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1455                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1456         };
1457         const char *model = getenv("model");
1458
1459         if (getenv("fdt_noauto")) {
1460                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1461                 return;
1462         }
1463
1464         /* Update partition nodes using info from mtdparts env var */
1465         puts("   Updating MTD partitions...\n");
1466         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1467
1468         if (!model) {
1469                 puts("invalid board info: Leaving FDT fully enabled\n");
1470                 return;
1471         }
1472         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1473
1474         /* board serial number */
1475         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1476                     strlen(getenv("serial#")) + 1);
1477
1478         /* board (model contains model from device-tree) */
1479         fdt_setprop(blob, 0, "board", info->model,
1480                     strlen((const char *)info->model) + 1);
1481
1482         /*
1483          * Peripheral Config:
1484          *  remove nodes by alias path if EEPROM config tells us the
1485          *  peripheral is not loaded on the board.
1486          */
1487         if (getenv("fdt_noconfig")) {
1488                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1489                 return;
1490         }
1491         cfg = econfig;
1492         while (cfg->name) {
1493                 if (!test_bit(cfg->bit, info->config)) {
1494                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1495                                                cfg->dtalias : cfg->name);
1496                 }
1497                 cfg++;
1498         }
1499 }
1500 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1501