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karo: fdt: fix panel-dpi support
[karo-tx-uboot.git] / board / gdsys / 405ep / 405ep.c
1 /*
2  * (C) Copyright 2010
3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <command.h>
10 #include <asm/processor.h>
11 #include <asm/io.h>
12 #include <asm/ppc4xx-gpio.h>
13 #include <asm/global_data.h>
14
15 #include "405ep.h"
16 #include <gdsys_fpga.h>
17
18 #define REFLECTION_TESTPATTERN 0xdede
19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
20
21 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
22 #define REFLECTION_TESTREG reflection_low
23 #else
24 #define REFLECTION_TESTREG reflection_high
25 #endif
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 int get_fpga_state(unsigned dev)
30 {
31         return gd->arch.fpga_state[dev];
32 }
33
34 void print_fpga_state(unsigned dev)
35 {
36         if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
37                 puts("       Waiting for FPGA-DONE timed out.\n");
38         if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
39                 puts("       FPGA reflection test failed.\n");
40 }
41
42 int board_early_init_f(void)
43 {
44         unsigned k;
45
46         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
47                 gd->arch.fpga_state[k] = 0;
48
49         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
50         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
51         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
52         mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
53         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
54         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
55         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
56
57         /*
58          * EBC Configuration Register: set ready timeout to 512 ebc-clks
59          * -> ca. 15 us
60          */
61         mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */
62         return 0;
63 }
64
65 int board_early_init_r(void)
66 {
67         unsigned k;
68         unsigned ctr;
69
70         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
71                 gd->arch.fpga_state[k] = 0;
72
73         /*
74          * reset FPGA
75          */
76         gd405ep_init();
77
78         gd405ep_set_fpga_reset(1);
79
80         gd405ep_setup_hw();
81
82         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
83                 ctr = 0;
84                 while (!gd405ep_get_fpga_done(k)) {
85                         udelay(100000);
86                         if (ctr++ > 5) {
87                                 gd->arch.fpga_state[k] |=
88                                         FPGA_STATE_DONE_FAILED;
89                                 break;
90                         }
91                 }
92         }
93
94         udelay(10);
95
96         gd405ep_set_fpga_reset(0);
97
98         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
99                 /*
100                  * wait for fpga out of reset
101                  */
102                 ctr = 0;
103                 while (1) {
104                         u16 val;
105
106                         FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
107
108                         FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
109                         if (val == REFLECTION_TESTPATTERN_INV)
110                                 break;
111
112                         udelay(100000);
113                         if (ctr++ > 5) {
114                                 gd->arch.fpga_state[k] |=
115                                         FPGA_STATE_REFLECTION_FAILED;
116                                 break;
117                         }
118                 }
119         }
120
121         return 0;
122 }