3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/osd.h"
19 #include "../common/mclink.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
30 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
31 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
34 UNITTYPE_MAIN_SERVER = 0,
35 UNITTYPE_MAIN_USER = 1,
36 UNITTYPE_VIDEO_SERVER = 2,
37 UNITTYPE_VIDEO_USER = 3,
58 COMPRESSION_TYPE1_DELTA = 1,
59 COMPRESSION_TYPE1_TYPE2_DELTA = 3,
80 CARRIER_SPEED_2_5G = 1,
85 MCFPGA_INIT_N = 1 << 1,
86 MCFPGA_PROGRAM_N = 1 << 2,
87 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
88 MCFPGA_RESET_N = 1 << 4,
96 unsigned int mclink_fpgacount;
97 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
99 static int setup_88e1518(const char *bus, unsigned char addr);
100 static int verify_88e1518(const char *bus, unsigned char addr);
102 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
111 res = mclink_send(fpga - 1, regoff, data);
113 printf("mclink_send reg %02lx data %04x returned %d\n",
123 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
129 *data = in_le16(reg);
132 if (fpga > mclink_fpgacount)
134 res = mclink_receive(fpga - 1, regoff, data);
136 printf("mclink_receive reg %02lx returned %d\n",
146 * Check Board Identity:
150 char *s = getenv("serial#");
166 static void print_fpga_info(unsigned int fpga)
172 unsigned hardware_version;
173 unsigned feature_compression;
174 unsigned feature_osd;
175 unsigned feature_audio;
176 unsigned feature_sysclock;
177 unsigned feature_ramconfig;
178 unsigned feature_carrier_speed;
179 unsigned feature_carriers;
180 unsigned feature_video_channels;
182 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
184 FPGA_GET_REG(0, versions, &versions);
185 FPGA_GET_REG(0, fpga_version, &fpga_version);
186 FPGA_GET_REG(0, fpga_features, &fpga_features);
188 unit_type = (versions & 0xf000) >> 12;
189 feature_compression = (fpga_features & 0xe000) >> 13;
190 feature_osd = fpga_features & (1<<11);
191 feature_audio = (fpga_features & 0x0600) >> 9;
192 feature_sysclock = (fpga_features & 0x0180) >> 7;
193 feature_ramconfig = (fpga_features & 0x0060) >> 5;
194 feature_carrier_speed = fpga_features & (1<<4);
195 feature_carriers = (fpga_features & 0x000c) >> 2;
196 feature_video_channels = fpga_features & 0x0003;
202 case UNITTYPE_MAIN_USER:
203 printf("Mainchannel");
206 case UNITTYPE_VIDEO_USER:
207 printf("Videochannel");
211 printf("UnitType %d(not supported)", unit_type);
215 if (unit_type == UNITTYPE_MAIN_USER) {
218 (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
221 (!!pca9698_get_value(0x20, 24) << 0)
222 | (!!pca9698_get_value(0x20, 25) << 1)
223 | (!!pca9698_get_value(0x20, 26) << 2)
224 | (!!pca9698_get_value(0x20, 27) << 3);
225 switch (hardware_version) {
227 printf(" HW-Ver 1.00,");
231 printf(" HW-Ver 1.04,");
235 printf(" HW-Ver 1.10,");
239 printf(" HW-Ver 1.20-1.21,");
243 printf(" HW-Ver 2.00,");
247 printf(" HW-Ver 2.10,");
251 printf(" HW-Ver 2.20,");
255 printf(" HW-Ver 2.30,");
259 printf(" HW-Ver %d(not supported),",
265 if (unit_type == UNITTYPE_VIDEO_USER) {
266 hardware_version = versions & 0x000f;
267 switch (hardware_version) {
269 printf(" HW-Ver 2.00,");
273 printf(" HW-Ver 2.10,");
277 printf(" HW-Ver %d(not supported),",
283 printf(" FPGA V %d.%02d\n features:",
284 fpga_version / 100, fpga_version % 100);
287 switch (feature_compression) {
288 case COMPRESSION_NONE:
289 printf(" no compression");
292 case COMPRESSION_TYPE1_DELTA:
293 printf(" type1-deltacompression");
296 case COMPRESSION_TYPE1_TYPE2_DELTA:
297 printf(" type1-deltacompression, type2-inlinecompression");
301 printf(" compression %d(not supported)", feature_compression);
305 printf(", %sosd", feature_osd ? "" : "no ");
307 switch (feature_audio) {
309 printf(", no audio");
313 printf(", audio tx");
317 printf(", audio rx");
321 printf(", audio rx+tx");
325 printf(", audio %d(not supported)", feature_audio);
331 switch (feature_sysclock) {
333 printf("clock 147.456 MHz");
337 printf("clock %d(not supported)", feature_sysclock);
341 switch (feature_ramconfig) {
343 printf(", RAM 32 bit DDR2");
347 printf(", RAM 32 bit DDR3");
351 printf(", RAM %d(not supported)", feature_ramconfig);
355 printf(", %d carrier(s) %s", feature_carriers,
356 feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
358 printf(", %d video channel(s)\n", feature_video_channels);
361 int last_stage_init(void)
365 unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
366 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
368 int feature_carrier_speed = fpga_features & (1<<4);
370 FPGA_GET_REG(0, fpga_features, &fpga_features);
375 /* wait for FPGA done */
376 for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
377 unsigned int ctr = 0;
379 if (i2c_probe(mclink_controllers[k]))
382 while (!(pca953x_get_val(mclink_controllers[k])
386 printf("no done for mclink_controller %d\n", k);
392 if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
393 miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
395 if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) {
396 printf("Fixup 88e1518 erratum on %s\n",
397 bb_miiphy_buses[0].name);
398 setup_88e1518(bb_miiphy_buses[0].name, 0);
402 /* wait for slave-PLLs to be up and running */
405 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
406 slaves = mclink_probe();
407 mclink_fpgacount = 0;
412 mclink_fpgacount = slaves;
414 for (k = 1; k <= slaves; ++k) {
415 FPGA_GET_REG(k, fpga_features, &fpga_features);
416 feature_carrier_speed = fpga_features & (1<<4);
420 if (feature_carrier_speed == CARRIER_SPEED_1G) {
421 miiphy_register(bb_miiphy_buses[k].name,
422 bb_miiphy_read, bb_miiphy_write);
423 if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
424 printf("Fixup 88e1518 erratum on %s\n",
425 bb_miiphy_buses[k].name);
426 setup_88e1518(bb_miiphy_buses[k].name, 0);
435 * provide access to fpga gpios (for I2C bitbang)
436 * (these may look all too simple but make iocon.h much more readable)
438 void fpga_gpio_set(unsigned int bus, int pin)
440 FPGA_SET_REG(bus, gpio.set, pin);
443 void fpga_gpio_clear(unsigned int bus, int pin)
445 FPGA_SET_REG(bus, gpio.clear, pin);
448 int fpga_gpio_get(unsigned int bus, int pin)
452 FPGA_GET_REG(bus, gpio.read, &val);
457 void gd405ep_init(void)
461 if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
462 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
463 gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
465 pca9698_direction_output(0x20, 4, 1);
469 void gd405ep_set_fpga_reset(unsigned state)
471 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
475 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
476 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
478 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
479 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
482 pca9698_set_value(0x20, 4, state ? 0 : 1);
486 void gd405ep_setup_hw(void)
489 * set "startup-finished"-gpios
491 gpio_write_bit(21, 0);
492 gpio_write_bit(22, 1);
495 int gd405ep_get_fpga_done(unsigned fpga)
497 int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
500 return in_le16((void *)LATCH2_BASE)
501 & CONFIG_SYS_FPGA_DONE(fpga);
503 return pca9698_get_value(0x20, 20);
507 * FPGA MII bitbang implementation
520 static int mii_dummy_init(struct bb_miiphy_bus *bus)
525 static int mii_mdio_active(struct bb_miiphy_bus *bus)
527 struct fpga_mii *fpga_mii = bus->priv;
530 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
532 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
537 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
539 struct fpga_mii *fpga_mii = bus->priv;
541 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
546 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
548 struct fpga_mii *fpga_mii = bus->priv;
551 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
553 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
560 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
563 struct fpga_mii *fpga_mii = bus->priv;
565 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
567 *v = ((gpio & GPIO_MDIO) != 0);
572 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
574 struct fpga_mii *fpga_mii = bus->priv;
577 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
579 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
584 static int mii_delay(struct bb_miiphy_bus *bus)
591 struct bb_miiphy_bus bb_miiphy_buses[] = {
594 .init = mii_dummy_init,
595 .mdio_active = mii_mdio_active,
596 .mdio_tristate = mii_mdio_tristate,
597 .set_mdio = mii_set_mdio,
598 .get_mdio = mii_get_mdio,
599 .set_mdc = mii_set_mdc,
601 .priv = &fpga_mii[0],
605 .init = mii_dummy_init,
606 .mdio_active = mii_mdio_active,
607 .mdio_tristate = mii_mdio_tristate,
608 .set_mdio = mii_set_mdio,
609 .get_mdio = mii_get_mdio,
610 .set_mdc = mii_set_mdc,
612 .priv = &fpga_mii[1],
616 .init = mii_dummy_init,
617 .mdio_active = mii_mdio_active,
618 .mdio_tristate = mii_mdio_tristate,
619 .set_mdio = mii_set_mdio,
620 .get_mdio = mii_get_mdio,
621 .set_mdc = mii_set_mdc,
623 .priv = &fpga_mii[2],
627 .init = mii_dummy_init,
628 .mdio_active = mii_mdio_active,
629 .mdio_tristate = mii_mdio_tristate,
630 .set_mdio = mii_set_mdio,
631 .get_mdio = mii_get_mdio,
632 .set_mdc = mii_set_mdc,
634 .priv = &fpga_mii[3],
638 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
639 sizeof(bb_miiphy_buses[0]);
642 * Workaround for erratum mentioned in 88E1518 release notes
645 static int verify_88e1518(const char *bus, unsigned char addr)
647 u16 phy_id1, phy_id2;
649 if (miiphy_read(bus, addr, 2, &phy_id1) ||
650 miiphy_read(bus, addr, 3, &phy_id2)) {
651 printf("Error reading from the PHY addr=%02x\n", addr);
655 if ((phy_id1 != 0x0141) || ((phy_id2 & 0xfff0) != 0x0dd0))
661 struct regfix_88e1518 {
664 } regfix_88e1518[] = {
679 static int setup_88e1518(const char *bus, unsigned char addr)
683 for (k = 0; k < ARRAY_SIZE(regfix_88e1518); ++k) {
684 if (miiphy_write(bus, addr,
685 regfix_88e1518[k].reg,
686 regfix_88e1518[k].data)) {
687 printf("Error writing to the PHY addr=%02x\n", addr);