2 * Copyright (C) 2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
4 * Copyright (C) 2009-2012 Genesi USA, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/iomux-mx51.h>
13 #include <asm/errno.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
19 #include <fsl_esdhc.h>
20 #include <power/pmic.h>
24 DECLARE_GLOBAL_DATA_PTR;
27 * Compile-time error checking
29 #ifndef CONFIG_MXC_SPI
30 #error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
36 * Note that we get these revisions here for convenience, but we only set
37 * up for the production model Smarttop (1.3) and Smartbook (2.0).
40 #define EFIKAMX_BOARD_REV_11 0x1
41 #define EFIKAMX_BOARD_REV_12 0x2
42 #define EFIKAMX_BOARD_REV_13 0x3
43 #define EFIKAMX_BOARD_REV_14 0x4
45 #define EFIKASB_BOARD_REV_13 0x1
46 #define EFIKASB_BOARD_REV_20 0x2
49 * Board identification
51 static u32 get_mx_rev(void)
64 * + note: r1.1 does not strap this pin properly so it needs to
65 * be hacked or ignored.
68 /* set to 1 in order to get correct value on board rev 1.1 */
69 gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
70 gpio_direction_input(IMX_GPIO_NR(3, 11));
71 gpio_direction_input(IMX_GPIO_NR(3, 16));
72 gpio_direction_input(IMX_GPIO_NR(3, 17));
74 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
75 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
76 rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
78 return (~rev & 0x7) + 1;
81 static iomux_v3_cfg_t const efikasb_revision_pads[] = {
82 MX51_PAD_EIM_CS3__GPIO2_28,
83 MX51_PAD_EIM_CS4__GPIO2_29,
86 static inline u32 get_sb_rev(void)
90 imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
91 ARRAY_SIZE(efikasb_revision_pads));
92 gpio_direction_input(IMX_GPIO_NR(2, 28));
93 gpio_direction_input(IMX_GPIO_NR(2, 29));
95 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
96 rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
101 inline uint32_t get_efikamx_rev(void)
103 if (machine_is_efikamx())
105 else if (machine_is_efikasb())
109 u32 get_board_rev(void)
111 return get_cpu_rev() | (get_efikamx_rev() << 8);
115 * DRAM initialization
119 /* dram_init must store complete ramsize in gd->ram_size */
120 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
128 static iomux_v3_cfg_t const efikamx_uart_pads[] = {
129 MX51_PAD_UART1_RXD__UART1_RXD,
130 MX51_PAD_UART1_TXD__UART1_TXD,
131 MX51_PAD_UART1_RTS__UART1_RTS,
132 MX51_PAD_UART1_CTS__UART1_CTS,
138 static iomux_v3_cfg_t const efikamx_spi_pads[] = {
139 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
140 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
141 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
142 MX51_PAD_CSPI1_SS0__GPIO4_24,
143 MX51_PAD_CSPI1_SS1__GPIO4_25,
144 MX51_PAD_GPIO1_6__GPIO1_6,
147 #define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
148 #define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
149 #define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
154 #ifdef CONFIG_MXC_SPI
155 int board_spi_cs_gpio(unsigned bus, unsigned cs)
157 return (bus == 0 && cs == 1) ? 121 : -1;
160 static void power_init(void)
163 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
167 ret = pmic_init(CONFIG_FSL_PMIC_BUS);
171 p = pmic_get("FSL_PMIC");
175 /* Write needed to Power Gate 2 register */
176 pmic_reg_read(p, REG_POWER_MISC, &val);
178 pmic_reg_write(p, REG_POWER_MISC, val);
180 /* Externally powered */
181 pmic_reg_read(p, REG_CHARGE, &val);
182 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
183 pmic_reg_write(p, REG_CHARGE, val);
185 /* power up the system first */
186 pmic_reg_write(p, REG_POWER_MISC, PWUP);
188 /* Set core voltage to 1.1V */
189 pmic_reg_read(p, REG_SW_0, &val);
190 val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
191 pmic_reg_write(p, REG_SW_0, val);
193 /* Setup VCC (SW2) to 1.25 */
194 pmic_reg_read(p, REG_SW_1, &val);
195 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
196 pmic_reg_write(p, REG_SW_1, val);
198 /* Setup 1V2_DIG1 (SW3) to 1.25 */
199 pmic_reg_read(p, REG_SW_2, &val);
200 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
201 pmic_reg_write(p, REG_SW_2, val);
204 /* Raise the core frequency to 800MHz */
205 writel(0x0, &mxc_ccm->cacrr);
207 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
208 /* Setup the switcher mode for SW1 & SW2*/
209 pmic_reg_read(p, REG_SW_4, &val);
210 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
211 (SWMODE_MASK << SWMODE2_SHIFT)));
212 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
213 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
214 pmic_reg_write(p, REG_SW_4, val);
216 /* Setup the switcher mode for SW3 & SW4 */
217 pmic_reg_read(p, REG_SW_5, &val);
218 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
219 (SWMODE_MASK << SWMODE4_SHIFT)));
220 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
221 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
222 pmic_reg_write(p, REG_SW_5, val);
224 /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
225 pmic_reg_read(p, REG_SETTING_0, &val);
226 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
227 val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
228 pmic_reg_write(p, REG_SETTING_0, val);
230 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
231 pmic_reg_read(p, REG_SETTING_1, &val);
232 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
233 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
234 pmic_reg_write(p, REG_SETTING_1, val);
236 /* Enable VGEN1, VGEN2, VDIG, VPLL */
237 pmic_reg_read(p, REG_MODE_0, &val);
238 val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
239 pmic_reg_write(p, REG_MODE_0, val);
241 /* Configure VGEN3 and VCAM regulators to use external PNP */
242 val = VGEN3CONFIG | VCAMCONFIG;
243 pmic_reg_write(p, REG_MODE_1, val);
246 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
247 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
248 VVIDEOEN | VAUDIOEN | VSDEN;
249 pmic_reg_write(p, REG_MODE_1, val);
251 pmic_reg_read(p, REG_POWER_CTL2, &val);
253 pmic_reg_write(p, REG_POWER_CTL2, val);
258 static inline void power_init(void) { }
264 #ifdef CONFIG_FSL_ESDHC
266 struct fsl_esdhc_cfg esdhc_cfg[2] = {
267 {MMC_SDHC1_BASE_ADDR},
268 {MMC_SDHC2_BASE_ADDR},
271 static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
272 MX51_PAD_SD1_CMD__SD1_CMD,
273 MX51_PAD_SD1_CLK__SD1_CLK,
274 MX51_PAD_SD1_DATA0__SD1_DATA0,
275 MX51_PAD_SD1_DATA1__SD1_DATA1,
276 MX51_PAD_SD1_DATA2__SD1_DATA2,
277 MX51_PAD_SD1_DATA3__SD1_DATA3,
278 MX51_PAD_GPIO1_1__SD1_WP,
281 #define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
283 static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
284 MX51_PAD_GPIO1_0__SD1_CD,
285 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
288 #define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
289 #define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
291 static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
292 MX51_PAD_SD2_CMD__SD2_CMD,
293 MX51_PAD_SD2_CLK__SD2_CLK,
294 MX51_PAD_SD2_DATA0__SD2_DATA0,
295 MX51_PAD_SD2_DATA1__SD2_DATA1,
296 MX51_PAD_SD2_DATA2__SD2_DATA2,
297 MX51_PAD_SD2_DATA3__SD2_DATA3,
298 MX51_PAD_GPIO1_7__SD2_WP,
299 MX51_PAD_GPIO1_8__SD2_CD,
302 #define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
303 #define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
305 static inline uint32_t efikamx_mmc_getcd(u32 base)
307 if (base == MMC_SDHC1_BASE_ADDR)
308 if (machine_is_efikamx())
309 return EFIKAMX_SDHC1_CD;
311 return EFIKASB_SDHC1_CD;
313 return EFIKASB_SDHC2_CD;
316 int board_mmc_getcd(struct mmc *mmc)
318 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
319 uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
320 int ret = !gpio_get_value(cd);
325 int board_mmc_init(bd_t *bis)
330 * All Efika MX boards use eSDHC1 with a common write-protect GPIO
332 imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
333 ARRAY_SIZE(efikamx_sdhc1_pads));
334 gpio_direction_input(EFIKAMX_SDHC1_WP);
337 * Smartbook and Smarttop differ on the location of eSDHC1
338 * carrier-detect GPIO
340 if (machine_is_efikamx()) {
341 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
342 gpio_direction_input(EFIKAMX_SDHC1_CD);
343 } else if (machine_is_efikasb()) {
344 imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
345 gpio_direction_input(EFIKASB_SDHC1_CD);
348 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
349 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
351 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
353 if (machine_is_efikasb()) {
355 imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
356 ARRAY_SIZE(efikasb_sdhc2_pads));
357 gpio_direction_input(EFIKASB_SDHC2_CD);
358 gpio_direction_input(EFIKASB_SDHC2_WP);
360 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
370 static iomux_v3_cfg_t const efikamx_pata_pads[] = {
371 MX51_PAD_NANDF_WE_B__PATA_DIOW,
372 MX51_PAD_NANDF_RE_B__PATA_DIOR,
373 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
374 MX51_PAD_NANDF_CLE__PATA_RESET_B,
375 MX51_PAD_NANDF_WP_B__PATA_DMACK,
376 MX51_PAD_NANDF_RB0__PATA_DMARQ,
377 MX51_PAD_NANDF_RB1__PATA_IORDY,
378 MX51_PAD_GPIO_NAND__PATA_INTRQ,
379 MX51_PAD_NANDF_CS2__PATA_CS_0,
380 MX51_PAD_NANDF_CS3__PATA_CS_1,
381 MX51_PAD_NANDF_CS4__PATA_DA_0,
382 MX51_PAD_NANDF_CS5__PATA_DA_1,
383 MX51_PAD_NANDF_CS6__PATA_DA_2,
384 MX51_PAD_NANDF_D15__PATA_DATA15,
385 MX51_PAD_NANDF_D14__PATA_DATA14,
386 MX51_PAD_NANDF_D13__PATA_DATA13,
387 MX51_PAD_NANDF_D12__PATA_DATA12,
388 MX51_PAD_NANDF_D11__PATA_DATA11,
389 MX51_PAD_NANDF_D10__PATA_DATA10,
390 MX51_PAD_NANDF_D9__PATA_DATA9,
391 MX51_PAD_NANDF_D8__PATA_DATA8,
392 MX51_PAD_NANDF_D7__PATA_DATA7,
393 MX51_PAD_NANDF_D6__PATA_DATA6,
394 MX51_PAD_NANDF_D5__PATA_DATA5,
395 MX51_PAD_NANDF_D4__PATA_DATA4,
396 MX51_PAD_NANDF_D3__PATA_DATA3,
397 MX51_PAD_NANDF_D2__PATA_DATA2,
398 MX51_PAD_NANDF_D1__PATA_DATA1,
399 MX51_PAD_NANDF_D0__PATA_DATA0,
405 #ifdef CONFIG_CMD_USB
406 extern void setup_iomux_usb(void);
408 static inline void setup_iomux_usb(void) { }
414 * Smarttop LED pad config is done in the DCD
417 #define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
418 #define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
419 #define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
421 static iomux_v3_cfg_t const efikasb_led_pads[] = {
422 MX51_PAD_GPIO1_3__GPIO1_3,
423 MX51_PAD_EIM_CS0__GPIO2_25,
426 #define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
427 #define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
430 * Board initialization
432 int board_early_init_f(void)
434 if (machine_is_efikasb()) {
435 imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
436 ARRAY_SIZE(efikasb_led_pads));
437 gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
438 gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
439 } else if (machine_is_efikamx()) {
441 * Set up GPIO directions for LEDs.
442 * IOMUX has been done in the DCD already.
443 * Turn the red LED on for pre-relocation code.
445 gpio_direction_output(EFIKAMX_LED_BLUE, 0);
446 gpio_direction_output(EFIKAMX_LED_GREEN, 0);
447 gpio_direction_output(EFIKAMX_LED_RED, 1);
451 * Both these pad configurations for UART and SPI are kind of redundant
452 * since they are the Power-On Defaults for the i.MX51. But, it seems we
453 * should make absolutely sure that they are set up correctly.
455 imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
456 ARRAY_SIZE(efikamx_uart_pads));
457 imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
458 ARRAY_SIZE(efikamx_spi_pads));
460 /* not technically required for U-Boot operation but do it anyway. */
461 gpio_direction_input(EFIKAMX_PMIC_IRQ);
462 /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
463 gpio_direction_output(EFIKAMX_SPI_SS0, 0);
464 gpio_direction_output(EFIKAMX_SPI_SS1, 1);
471 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
476 int board_late_init(void)
478 if (machine_is_efikamx()) {
480 * Set up Blue LED for "In U-Boot" status.
481 * We're all relocated and ready to U-Boot!
483 gpio_set_value(EFIKAMX_LED_RED, 0);
484 gpio_set_value(EFIKAMX_LED_GREEN, 0);
485 gpio_set_value(EFIKAMX_LED_BLUE, 1);
490 imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
491 ARRAY_SIZE(efikamx_pata_pads));
499 u32 rev = get_efikamx_rev();
501 printf("Board: Genesi Efika MX ");
502 if (machine_is_efikamx())
503 printf("Smarttop (1.%i)\n", rev & 0xf);
504 else if (machine_is_efikasb())
505 printf("Smartbook\n");