3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/clock.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/sys_proto.h>
32 DECLARE_GLOBAL_DATA_PTR;
36 /* dram_init must store complete ramsize in gd->ram_size */
37 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
45 gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
46 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
51 int board_early_init_f(void)
54 static const struct mxc_weimcs cs0 = {
55 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
56 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
57 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
58 CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
59 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
60 CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
63 /* CS1: Network Controller */
64 static const struct mxc_weimcs cs1 = {
65 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
66 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
67 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
68 CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
69 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
70 CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
74 static const struct mxc_weimcs cs4 = {
75 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
76 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
77 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
78 CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
79 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
80 CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
83 mxc_setup_weimcs(0, &cs0);
84 mxc_setup_weimcs(1, &cs1);
85 mxc_setup_weimcs(4, &cs4);
87 /* setup pins for UART1 */
88 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
89 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
90 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
91 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
93 /* setup pins for I2C2 (for EEPROM, RTC) */
94 mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
95 mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
100 #ifdef CONFIG_BOARD_LATE_INIT
101 int board_late_init(void)
103 #ifdef CONFIG_S6E63D6
104 struct s6e63d6 data = {
106 * See comment in mxc_spi.c::decode_cs() for .cs field format.
107 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
108 * 2 of the SPI controller #1, since it is unused.
117 mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
118 mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
119 mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
120 mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
121 mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
122 mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
123 mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
125 /* start SPI1 clock */
126 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
129 /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
130 mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
132 /* SPI1 CS2 is free */
133 ret = s6e63d6_init(&data);
138 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
139 * OLED display connected to a S6E63D6 SPI display controller in the
142 s6e63d6_index(&data, 2);
143 s6e63d6_param(&data, 0x0182);
144 s6e63d6_index(&data, 3);
145 s6e63d6_param(&data, 0x8130);
146 s6e63d6_index(&data, 0x10);
147 s6e63d6_param(&data, 0x0000);
148 s6e63d6_index(&data, 5);
149 s6e63d6_param(&data, 0x0001);
150 s6e63d6_index(&data, 0x22);
156 int checkboard (void)
158 printf("Board: Phytec phyCore i.MX31\n");
162 int board_eth_init(bd_t *bis)
165 #ifdef CONFIG_SMC911X
166 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);