2 * Memory sub-system initialization code for INCA-IP development board.
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/regdef.h>
30 #define EBU_MODUL_BASE 0xB8000200
31 #define EBU_CLC(value) 0x0000(value)
32 #define EBU_CON(value) 0x0010(value)
33 #define EBU_ADDSEL0(value) 0x0020(value)
34 #define EBU_ADDSEL1(value) 0x0024(value)
35 #define EBU_ADDSEL2(value) 0x0028(value)
36 #define EBU_BUSCON0(value) 0x0060(value)
37 #define EBU_BUSCON1(value) 0x0064(value)
38 #define EBU_BUSCON2(value) 0x0068(value)
40 #define MC_MODUL_BASE 0xBF800000
41 #define MC_ERRCAUSE(value) 0x0100(value)
42 #define MC_ERRADDR(value) 0x0108(value)
43 #define MC_IOGP(value) 0x0800(value)
44 #define MC_SELFRFSH(value) 0x0A00(value)
45 #define MC_CTRLENA(value) 0x1000(value)
46 #define MC_MRSCODE(value) 0x1008(value)
47 #define MC_CFGDW(value) 0x1010(value)
48 #define MC_CFGPB0(value) 0x1018(value)
49 #define MC_LATENCY(value) 0x1038(value)
50 #define MC_TREFRESH(value) 0x1040(value)
52 #if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */
53 #define CGU_MODUL_BASE 0xBF107000
54 #define CGU_PLL1CR(value) 0x0008(value)
55 #define CGU_DIVCR(value) 0x0010(value)
56 #define CGU_MUXCR(value) 0x0014(value)
57 #define CGU_PLL1SR(value) 0x000C(value)
63 /* EBU Initialization for the Flash CS0 and CS2.
68 sw t1, EBU_ADDSEL0(t0)
70 #if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */
72 sw t1, EBU_BUSCON0(t0) /* value set up by magic flash word */
73 sw t1, EBU_BUSCON2(t0)
75 lw t1, EBU_BUSCON0(t0) /* value set up by magic flash word */
76 sw t1, EBU_BUSCON2(t0)
80 sw t1, EBU_ADDSEL2(t0)
82 /* Need to initialize CS1 too, so as to to prevent overlapping with
86 sw t1, EBU_ADDSEL1(t0)
88 #if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */
93 sw t1, EBU_BUSCON1(t0)
95 #if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */
100 sw t1, CGU_PLL1CR(t0)
103 lw t1, CGU_PLL1SR(t0)
110 /* SDRAM Initialization.
114 /* Clear Error log registers */
115 sw zero, MC_ERRCAUSE(t0)
116 sw zero, MC_ERRADDR(t0)
118 /* Set clock ratio to 1:1 */
119 li t1, 0x03 /* clkrat=1:1, rddel=3 */
122 /* Clear Power-down registers */
123 sw zero, MC_SELFRFSH(t0)
125 /* Set CAS Latency */
126 li t1, 0x00000020 /* CL = 2 */
127 sw t1, MC_MRSCODE(t0)
129 /* Set word width to 16 bit */
133 /* Set CS0 to SDRAM parameters */
137 /* Set SDRAM latency parameters */
138 li t1, 0x00026325 /* BC PC100 */
139 sw t1, MC_LATENCY(t0)
141 /* Set SDRAM refresh rate */
142 li t1, 0x00000C30 /* 4K/64ms @ 100MHz */
143 sw t1, MC_TREFRESH(t0)
145 /* Finally enable the controller */
147 sw t1, MC_CTRLENA(t0)