2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
4 * NOTE: I haven't clean this up considerably, just enough to get it
5 * running. See hal_platform_setup.h for the source. See
6 * board/cradle/memsetup.S for another PXA250 setup that is
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/pxa-regs.h>
32 DRAM_SIZE: .long CFG_DRAM_SIZE
34 /* wait for coprocessor write complete */
36 mrc p15,0,\reg,c2,c0,0
54 /* Set up GPIO pins first ----------------------------------------- */
57 ldr r1, =CFG_GPSR0_VAL
61 ldr r1, =CFG_GPSR1_VAL
65 ldr r1, =CFG_GPSR2_VAL
69 ldr r1, =CFG_GPCR0_VAL
73 ldr r1, =CFG_GPCR1_VAL
77 ldr r1, =CFG_GPCR2_VAL
81 ldr r1, =CFG_GPDR0_VAL
85 ldr r1, =CFG_GPDR1_VAL
89 ldr r1, =CFG_GPDR2_VAL
93 ldr r1, =CFG_GAFR0_L_VAL
97 ldr r1, =CFG_GAFR0_U_VAL
101 ldr r1, =CFG_GAFR1_L_VAL
105 ldr r1, =CFG_GAFR1_U_VAL
109 ldr r1, =CFG_GAFR2_L_VAL
113 ldr r1, =CFG_GAFR2_U_VAL
116 ldr r0, =PSSR /* enable GPIO pins */
117 ldr r1, =CFG_PSSR_VAL
120 /* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
121 /* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
122 /* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
123 /* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
125 /* ldr r1, =LED_BLANK */
127 /* str r0, [r1] / turn on hex leds */
131 /* ldr r0, =0xB0070001 */
133 /* str r0, [r1] / hex display */
136 /* ---------------------------------------------------------------- */
137 /* Enable memory interface */
139 /* The sequence below is based on the recommended init steps */
140 /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
142 /* ---------------------------------------------------------------- */
144 /* ---------------------------------------------------------------- */
145 /* Step 1: Wait for at least 200 microsedonds to allow internal */
146 /* clocks to settle. Only necessary after hard reset... */
147 /* FIXME: can be optimized later */
148 /* ---------------------------------------------------------------- */
150 ldr r3, =OSCR /* reset the OS Timer Count to zero */
153 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
154 /* so 0x300 should be plenty */
162 ldr r1, =MEMC_BASE /* get memory controller base addr. */
164 /* ---------------------------------------------------------------- */
165 /* Step 2a: Initialize Asynchronous static memory controller */
166 /* ---------------------------------------------------------------- */
168 /* MSC registers: timing, bus width, mem type */
171 ldr r2, =CFG_MSC0_VAL
172 str r2, [r1, #MSC0_OFFSET]
173 ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
174 /* that data latches */
176 ldr r2, =CFG_MSC1_VAL
177 str r2, [r1, #MSC1_OFFSET]
178 ldr r2, [r1, #MSC1_OFFSET]
181 ldr r2, =CFG_MSC2_VAL
182 str r2, [r1, #MSC2_OFFSET]
183 ldr r2, [r1, #MSC2_OFFSET]
185 /* ---------------------------------------------------------------- */
186 /* Step 2b: Initialize Card Interface */
187 /* ---------------------------------------------------------------- */
189 /* MECR: Memory Expansion Card Register */
190 ldr r2, =CFG_MECR_VAL
191 str r2, [r1, #MECR_OFFSET]
192 ldr r2, [r1, #MECR_OFFSET]
194 /* MCMEM0: Card Interface slot 0 timing */
195 ldr r2, =CFG_MCMEM0_VAL
196 str r2, [r1, #MCMEM0_OFFSET]
197 ldr r2, [r1, #MCMEM0_OFFSET]
199 /* MCMEM1: Card Interface slot 1 timing */
200 ldr r2, =CFG_MCMEM1_VAL
201 str r2, [r1, #MCMEM1_OFFSET]
202 ldr r2, [r1, #MCMEM1_OFFSET]
204 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
205 ldr r2, =CFG_MCATT0_VAL
206 str r2, [r1, #MCATT0_OFFSET]
207 ldr r2, [r1, #MCATT0_OFFSET]
209 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
210 ldr r2, =CFG_MCATT1_VAL
211 str r2, [r1, #MCATT1_OFFSET]
212 ldr r2, [r1, #MCATT1_OFFSET]
214 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
215 ldr r2, =CFG_MCIO0_VAL
216 str r2, [r1, #MCIO0_OFFSET]
217 ldr r2, [r1, #MCIO0_OFFSET]
219 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
220 ldr r2, =CFG_MCIO1_VAL
221 str r2, [r1, #MCIO1_OFFSET]
222 ldr r2, [r1, #MCIO1_OFFSET]
224 /* ---------------------------------------------------------------- */
225 /* Step 2c: Write FLYCNFG FIXME: what's that??? */
226 /* ---------------------------------------------------------------- */
228 /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
229 adr r3, mem_init /* r0 <- current position of code */
231 cmp r3, r2 /* skip init if in place */
235 /* ---------------------------------------------------------------- */
236 /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
237 /* ---------------------------------------------------------------- */
239 /* Before accessing MDREFR we need a valid DRI field, so we set */
240 /* this to power on defaults + DIR field. */
243 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
244 ldr r4, [r1, #MDREFR_OFFSET]
247 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
248 ldr r4, [r1, #MDREFR_OFFSET]
250 /* Note: preserve the mdrefr value in r4 */
253 /* ---------------------------------------------------------------- */
254 /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
255 /* ---------------------------------------------------------------- */
257 /* Initialize SXCNFG register. Assert the enable bits */
259 /* Write SXMRS to cause an MRS command to all enabled banks of */
260 /* synchronous static memory. Note that SXLCR need not be written */
263 /* FIXME: we use async mode for now */
266 /* ---------------------------------------------------------------- */
267 /* Step 4: Initialize SDRAM */
268 /* ---------------------------------------------------------------- */
270 /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */
271 /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
273 orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN)
275 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
276 ldr r4, [r1, #MDREFR_OFFSET]
279 /* Step 4b: de-assert MDREFR:SLFRSH. */
281 bic r4, r4, #(MDREFR_SLFRSH)
283 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
284 ldr r4, [r1, #MDREFR_OFFSET]
287 /* Step 4c: assert MDREFR:E1PIN and E0PIO */
289 orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
291 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
292 ldr r4, [r1, #MDREFR_OFFSET]
295 /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
296 /* configure but not enable each SDRAM partition pair. */
298 ldr r4, =CFG_MDCNFG_VAL
299 bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
301 str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
302 ldr r4, [r1, #MDCNFG_OFFSET]
305 /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
308 ldr r3, =OSCR /* reset the OS Timer Count to zero */
311 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
312 /* so 0x300 should be plenty */
319 /* Step 4f: Trigger a number (usually 8) refresh cycles by */
320 /* attempting non-burst read or write accesses to disabled */
321 /* SDRAM, as commonly specified in the power up sequence */
322 /* documented in SDRAM data sheets. The address(es) used */
323 /* for this purpose must not be cacheable. */
325 /* There should 9 writes, since the first write doesn't */
326 /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
327 /* PXA210 Processors Specification Update, */
328 /* Jan 2003, Errata #116, page 30. */
331 ldr r3, =CFG_DRAM_BASE
342 /* Step 4g: Write MDCNFG with enable bits asserted */
343 /* (MDCNFG:DEx set to 1). */
345 ldr r3, [r1, #MDCNFG_OFFSET]
346 orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
347 str r3, [r1, #MDCNFG_OFFSET]
349 /* Step 4h: Write MDMRS. */
351 ldr r2, =CFG_MDMRS_VAL
352 str r2, [r1, #MDMRS_OFFSET]
355 /* We are finished with Intel's memory controller initialisation */
357 /* ---------------------------------------------------------------- */
358 /* Disable (mask) all interrupts at interrupt controller */
359 /* ---------------------------------------------------------------- */
363 mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
367 ldr r2, =ICMR /* mask all interrupts at the controller */
371 /* ---------------------------------------------------------------- */
372 /* Clock initialisation */
373 /* ---------------------------------------------------------------- */
377 /* Disable the peripheral clocks, and set the core clock frequency */
378 /* (hard-coding at 398.12MHz for now). */
380 /* Turn Off ALL on-chip peripheral clocks for re-configuration */
381 /* Note: See label 'ENABLECLKS' for the re-enabling */
387 /* default value in case no valid rotary switch setting is found */
388 ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
390 /* ... and write the core clock config register */
394 /* enable the 32Khz oscillator for RTC and PowerManager */
400 /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
407 /* ---------------------------------------------------------------- */
409 /* ---------------------------------------------------------------- */
411 /* Save SDRAM size */
415 /* Interrupt init: Mask all interrupts */
416 ldr r0, =ICMR /* enable no sources */
423 /*Disable software and data breakpoints */
425 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
426 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
427 mcr p15,0,r0,c14,c4,0 /* dbcon */
429 /*Enable all debug functionality */
431 mcr p14,0,r0,c10,c0,0 /* dcsr */
434 /* ---------------------------------------------------------------- */
436 /* ---------------------------------------------------------------- */