3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2009
9 * Modified for InterControl digsyMTC MPC5200 board by
10 * Frank Bodammer, GCD Hard- & Software GmbH,
11 * frank.bodammer@gcd-solutions.de
14 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/processor.h>
42 #if defined(CONFIG_DIGSY_REV5)
43 #include "is45s16800a2.h"
44 #include <mtd/cfi_flash.h>
47 #include "is42s16800a-7t.h"
50 #include <fdt_support.h>
53 DECLARE_GLOBAL_DATA_PTR;
55 extern int usb_cpu_init(void);
57 #if defined(CONFIG_DIGSY_REV5)
59 * The M29W128GH needs a specail reset command function,
60 * details see the doc/README.cfi file
62 void flash_cmd_reset(flash_info_t *info)
64 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
68 #ifndef CONFIG_SYS_RAMBOOT
69 static void sdram_start(int hi_addr)
71 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
72 long control = SDRAM_CONTROL | hi_addr_bit;
74 /* unlock mode register */
75 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
77 /* precharge all banks */
78 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
81 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
83 /* set mode register */
84 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
86 /* normal operation */
87 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
92 * ATTENTION: Although partially referenced initdram does NOT make real use
93 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
94 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
97 phys_size_t initdram(int board_type)
102 #ifndef CONFIG_SYS_RAMBOOT
105 /* setup SDRAM chip selects */
106 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
107 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
109 /* setup config registers */
110 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
111 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
113 /* find RAM size using SDRAM CS0 only */
115 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
117 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
125 /* memory smaller than 1MB is impossible */
126 if (dramsize < (1 << 20))
129 /* set SDRAM CS0 size according to the amount of RAM found */
131 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
132 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
134 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
137 /* let SDRAM CS1 start right after CS0 */
138 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
140 /* find RAM size using SDRAM CS1 only */
141 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
145 /* memory smaller than 1MB is impossible */
146 if (dramsize2 < (1 << 20))
149 /* set SDRAM CS1 size according to the amount of RAM found */
151 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
152 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
154 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
157 #else /* CONFIG_SYS_RAMBOOT */
159 /* retrieve size of memory connected to SDRAM CS0 */
160 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
161 if (dramsize >= 0x13)
162 dramsize = (1 << (dramsize - 0x13)) << 20;
166 /* retrieve size of memory connected to SDRAM CS1 */
167 dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
168 if (dramsize2 >= 0x13)
169 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
173 #endif /* CONFIG_SYS_RAMBOOT */
176 * On MPC5200B we need to set the special configuration delay in the
177 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
178 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
180 * "The SDelay should be written to a value of 0x00000004. It is
181 * required to account for changes caused by normal wafer processing
186 if ((SVR_MJREV(svr) >= 2) &&
187 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
188 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
190 return dramsize + dramsize2;
196 int i = getenv_f("serial#", buf, sizeof(buf));
198 puts ("Board: InterControl digsyMTC");
199 #if defined(CONFIG_DIGSY_REV5)
211 #if defined(CONFIG_VIDEO)
213 #define GPIO_USB1_0 0x00010000 /* Power-On pin */
214 #define GPIO_USB1_9 0x08 /* PX_~EN pin */
216 #define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
217 #define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
218 #define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
219 #define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
221 #define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
223 static void exbo_hw_init(void)
225 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
226 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
227 struct mpc5xxx_wu_gpio *wu_gpio =
228 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
231 /* 1st, check if extension board is present */
232 if (i2c_read(CONFIG_SYS_EXBO_EE_I2C_ADDRESS, 0, 1, &val, 1))
235 /* configure IrDA pins (PSC6 port) as gpios */
236 gpio->port_config &= 0xFF8FFFFF;
238 /* Init for USB1_0, EE_CLK and EE_DI - Low */
239 setbits_be32(&gpio->simple_ddr,
240 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
241 clrbits_be32(&gpio->simple_ode,
242 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
243 clrbits_be32(&gpio->simple_dvo,
244 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
245 setbits_be32(&gpio->simple_gpioe,
246 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
248 /* Init for EE_DO, EE_CTS - Input */
249 clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
250 setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
252 /* Init for PX_~EN (USB1_9) - High */
253 clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
254 setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
255 clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
256 setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
257 setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
259 /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
260 out_be32(&gpt[0].emsr, GPT_GPIO_ON);
261 /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
262 out_be32(&gpt[1].emsr, GPT_GPIO_ON);
264 /* Power-On camera supply */
265 setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
268 static inline void exbo_hw_init(void) {}
269 #endif /* CONFIG_VIDEO */
271 int board_early_init_r(void)
273 #ifdef CONFIG_MPC52XX_SPI
274 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
277 * Now, when we are in RAM, enable flash write access for detection
278 * process. Note that CS_BOOT cannot be cleared when executing in
281 /* disable CS_BOOT */
282 clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
284 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
286 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
290 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
291 /* Low level USB init, required for proper kernel operation */
294 #ifdef CONFIG_MPC52XX_SPI
295 /* GPT 6 Output Enable */
296 out_be32(&gpt[6].emsr, 0x00000034);
297 /* GPT 7 Output Enable */
298 out_be32(&gpt[7].emsr, 0x00000034);
304 void board_get_enetaddr (uchar * enet)
307 ushort addr_of_eth_addr = 0;
309 ushort len_sys_cfg = 0;
311 /* check identification word */
312 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
313 if (read != EEPROM_IDENT)
316 /* calculate offset of config area */
317 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
318 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
319 (uchar *)&len_sys_cfg, 2);
320 addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
321 if (addr_of_eth_addr >= EEPROM_LEN)
324 eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
327 int misc_init_r(void)
331 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
332 board_get_enetaddr(enetaddr);
333 eth_setenv_enetaddr("ethaddr", enetaddr);
340 static struct pci_controller hose;
342 extern void pci_mpc5xxx_init(struct pci_controller *);
344 void pci_init_board(void)
346 pci_mpc5xxx_init(&hose);
350 #ifdef CONFIG_CMD_IDE
352 #ifdef CONFIG_IDE_RESET
354 void init_ide_reset(void)
356 debug ("init_ide_reset\n");
358 /* set gpio output value to 1 */
359 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
360 /* open drain output */
361 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
362 /* direction output */
363 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
365 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
369 void ide_set_reset(int idereset)
371 debug ("ide_reset(%d)\n", idereset);
373 /* set gpio output value to 0 */
374 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
375 /* open drain output */
376 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
377 /* direction output */
378 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
380 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
384 /* set gpio output value to 1 */
385 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
386 /* open drain output */
387 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
388 /* direction output */
389 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
391 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
393 #endif /* CONFIG_IDE_RESET */
394 #endif /* CONFIG_CMD_IDE */
396 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
397 static void ft_delete_node(void *fdt, const char *compat)
402 off = fdt_node_offset_by_compatible(fdt, -1, compat);
404 printf("Could not find %s node.\n", compat);
408 ret = fdt_del_node(fdt, off);
410 printf("Could not delete %s node.\n", compat);
412 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
413 static void ft_adapt_flash_base(void *blob)
415 flash_info_t *dev = &flash_info[0];
417 struct fdt_property *prop;
421 off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
423 printf("Could not find fsl,mpc5200b-lpb node.\n");
427 /* found compatible property */
428 prop = fdt_get_property_w(blob, off, "ranges", &len);
430 reg = reg2 = (u32 *)&prop->data[0];
432 reg[2] = dev->start[0];
434 fdt_setprop(blob, off, "ranges", reg2, len);
436 printf("Could not find ranges\n");
439 extern ulong flash_get_size (phys_addr_t base, int banknum);
441 /* Update the Flash Baseaddr settings */
442 int update_flash_size (int flash_size)
444 volatile struct mpc5xxx_mmap_ctl *mm =
445 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
449 unsigned long base = 0x0;
450 u32 *cs_reg = (u32 *)&mm->cs0_start;
452 for (i = 0; i < 2; i++) {
453 dev = &flash_info[i];
456 /* calculate new base addr for this chipselect */
458 out_be32(cs_reg, START_REG(base));
460 out_be32(cs_reg, STOP_REG(base, dev->size));
462 /* recalculate the sectoraddr in the cfi driver */
463 size += flash_get_size(base, i);
466 flash_protect_default();
467 gd->bd->bi_flashstart = base;
470 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
472 void ft_board_setup(void *blob, bd_t *bd)
474 int phy_addr = CONFIG_PHY_ADDR;
475 char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
477 ft_cpu_setup(blob, bd);
479 * There are 2 RTC nodes in the DTS, so remove
480 * the unneeded node here.
482 #if defined(CONFIG_DIGSY_REV5)
483 ft_delete_node(blob, "dallas,ds1339");
485 ft_delete_node(blob, "mc,rv3029c2");
487 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
488 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
489 /* Update reg property in all nor flash nodes too */
490 fdt_fixup_nor_flash_size(blob);
492 ft_adapt_flash_base(blob);
494 /* fix up the phy address */
495 do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
497 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */