2 * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
22 #include <fdt_support.h>
28 #include <linux/list.h>
32 #include <asm/arch/iomux.h>
33 #include <asm/arch/iomux-mx28.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/sys_proto.h>
38 #include "../common/karo.h"
40 DECLARE_GLOBAL_DATA_PTR;
42 #define TX28_LCD_PWR_GPIO MXS_PAD_TO_GPIO(MX28_PAD_LCD_ENABLE__GPIO_1_31)
43 #define TX28_LCD_RST_GPIO MXS_PAD_TO_GPIO(MX28_PAD_LCD_RESET__GPIO_3_30)
44 #define TX28_LCD_BACKLIGHT_GPIO MXS_PAD_TO_GPIO(MX28_PAD_PWM0__GPIO_3_16)
46 #define TX28_USBH_VBUSEN_GPIO MXS_PAD_TO_GPIO(MX28_PAD_SPDIF__GPIO_3_27)
47 #define TX28_USBH_OC_GPIO MXS_PAD_TO_GPIO(MX28_PAD_JTAG_RTCK__GPIO_4_20)
48 #define TX28_USBOTG_VBUSEN_GPIO MXS_PAD_TO_GPIO(MX28_PAD_GPMI_CE2N__GPIO_0_18)
49 #define TX28_USBOTG_OC_GPIO MXS_PAD_TO_GPIO(MX28_PAD_GPMI_CE3N__GPIO_0_19)
50 #define TX28_USBOTG_ID_GPIO MXS_PAD_TO_GPIO(MX28_PAD_PWM2__GPIO_3_18)
52 #define TX28_LED_GPIO MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RXD3__GPIO_4_10)
54 #define STK5_CAN_XCVR_PAD MX28_PAD_LCD_D00__GPIO_1_0
55 #define STK5_CAN_XCVR_GPIO MXS_PAD_TO_GPIO(STK5_CAN_XCVR_PAD)
57 #define ENET_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
58 #define GPIO_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
59 #define I2C_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
61 #ifndef CONFIG_CONS_INDEX
62 struct serial_device *default_serial_console(void)
68 static const struct gpio tx28_gpios[] = {
69 { TX28_USBH_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBH VBUSEN", },
70 { TX28_USBH_OC_GPIO, GPIOFLAG_INPUT, "USBH OC", },
71 { TX28_USBOTG_VBUSEN_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
72 { TX28_USBOTG_OC_GPIO, GPIOFLAG_INPUT, "USBOTG OC", },
73 { TX28_USBOTG_ID_GPIO, GPIOFLAG_INPUT, "USBOTG ID", },
76 static const iomux_cfg_t tx28_pads[] = {
77 /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
78 MX28_PAD_I2C0_SCL__I2C0_SCL | I2C_PAD_CTRL,
79 MX28_PAD_I2C0_SDA__I2C0_SDA | I2C_PAD_CTRL,
82 MX28_PAD_SPDIF__GPIO_3_27,
83 MX28_PAD_JTAG_RTCK__GPIO_4_20,
85 /* USBOTG VBUSEN, OC, ID */
86 MX28_PAD_GPMI_CE2N__GPIO_0_18,
87 MX28_PAD_GPMI_CE3N__GPIO_0_19,
88 MX28_PAD_PWM2__GPIO_3_18,
95 /* provide at least _some_ sort of randomness */
98 static u32 random __attribute__((section("data")));
100 static inline void random_init(void)
102 struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
106 for (i = 0; i < MAX_LOOPS; i++) {
107 u32 hclk = readl(&digctl_regs->hw_digctl_hclkcount);
108 u32 entropy = readl(&digctl_regs->hw_digctl_entropy);
109 u32 usec = readl(&digctl_regs->hw_digctl_microseconds);
111 seed = get_timer(hclk ^ entropy ^ usec ^ random ^ seed);
117 #define RTC_PERSISTENT0_CLK32_MASK (RTC_PERSISTENT0_CLOCKSOURCE | \
118 RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
119 static u32 boot_cause __attribute__((section("data")));
121 int board_early_init_f(void)
123 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
129 /* IO0 clock at 480MHz */
130 mxs_set_ioclk(MXC_IOCLK0, 480000);
131 /* IO1 clock at 480MHz */
132 mxs_set_ioclk(MXC_IOCLK1, 480000);
134 /* SSP0 clock at 96MHz */
135 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
136 /* SSP2 clock at 96MHz */
137 mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
139 gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
140 mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
142 while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
143 RTC_STAT_STALE_REGS_PERSISTENT0) {
148 boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
149 if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
150 RTC_PERSISTENT0_CLK32_MASK) {
151 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
153 writel(RTC_PERSISTENT0_CLK32_MASK,
154 &rtc_regs->hw_rtc_persistent0_set);
159 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
166 printf("CTRL-C detected; safeboot enabled\n");
168 /* Address of boot parameters */
169 #ifdef CONFIG_OF_LIBFDT
170 gd->bd->bi_arch_number = -1;
172 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
178 return mxs_dram_init();
181 #ifdef CONFIG_CMD_MMC
182 static int tx28_mmc_wp(int dev_no)
187 int board_mmc_init(bd_t *bis)
189 return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL);
191 #endif /* CONFIG_CMD_MMC */
193 #ifdef CONFIG_FEC_MXC
194 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
196 #ifndef CONFIG_TX28_S
197 #define FEC_MAX_IDX 1
199 #define FEC_MAX_IDX 0
205 static int fec_get_mac_addr(int index)
208 struct mxs_ocotp_regs *ocotp_regs =
209 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
210 u32 *cust = &ocotp_regs->hw_ocotp_cust0;
212 char env_name[] = "eth.addr";
216 if (index < 0 || index > FEC_MAX_IDX)
219 /* set this bit to open the OTP banks for reading */
220 writel(OCOTP_CTRL_RD_BANK_OPEN,
221 &ocotp_regs->hw_ocotp_ctrl_set);
223 /* wait until OTP contents are readable */
224 while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
230 for (i = 0; i < sizeof(mac); i++) {
231 int shift = 24 - i % 4 * 8;
234 val = readl(&cust[index * 8 + i]);
235 mac[i] = val >> shift;
237 if (!is_valid_ethaddr(mac)) {
239 printf("No valid MAC address programmed\n");
244 printf("MAC addr from fuse: %pM\n", mac);
245 snprintf(env_name, sizeof(env_name), "ethaddr");
247 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
249 eth_setenv_enetaddr(env_name, mac);
253 static inline int tx28_fec1_enabled(void)
261 off = fdt_path_offset(gd->fdt_blob, "ethernet1");
265 status = fdt_getprop(gd->fdt_blob, off, "status", NULL);
266 return status && (strcmp(status, "okay") == 0);
269 static void tx28_init_mac(void)
273 ret = fec_get_mac_addr(0);
275 printf("Failed to read FEC0 MAC address from OCOTP\n");
279 if (tx28_fec1_enabled()) {
280 ret = fec_get_mac_addr(1);
282 printf("Failed to read FEC1 MAC address from OCOTP\n");
289 static inline void tx28_init_mac(void)
292 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
294 static const iomux_cfg_t tx28_fec_pads[] = {
295 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | ENET_PAD_CTRL,
296 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | ENET_PAD_CTRL,
297 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | ENET_PAD_CTRL,
300 static struct gpio tx28_fec_strap_gpios[] = {
301 /* first entry must be RESET pin */
302 { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RX_CLK__GPIO_4_13),
303 GPIOFLAG_OUTPUT_INIT_LOW, "PHY Reset", },
305 { MXS_PAD_TO_GPIO(MX28_PAD_PWM4__GPIO_3_29),
306 GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Power", },
308 /* Pull strap pins to high */
309 { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RX_EN__GPIO_4_2),
310 GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Mode0", },
311 { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RXD0__GPIO_4_3),
312 GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Mode1", },
313 { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_RXD1__GPIO_4_4),
314 GPIOFLAG_OUTPUT_INIT_HIGH, "PHY Mode2", },
316 { MXS_PAD_TO_GPIO(MX28_PAD_ENET0_TX_CLK__GPIO_4_5),
317 GPIOFLAG_INPUT, "PHY INT", },
320 int board_eth_init(bd_t *bis)
324 /* Reset the external phy */
325 ret = gpio_request_array(tx28_fec_strap_gpios,
326 ARRAY_SIZE(tx28_fec_strap_gpios));
328 printf("Failed to request FEC GPIOs: %d\n", ret);
331 gpio_set_value(tx28_fec_strap_gpios[0].gpio, 1);
334 mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
336 ret = cpu_eth_init(bis);
338 printf("cpu_eth_init() failed: %d\n", ret);
342 #ifndef CONFIG_TX28_S
343 if (getenv("ethaddr")) {
344 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
346 printf("FEC MXS: Unable to init FEC0\n");
351 if (getenv("eth1addr")) {
352 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
354 printf("FEC MXS: Unable to init FEC1\n");
359 if (getenv("ethaddr")) {
360 ret = fecmxc_initialize(bis);
362 printf("FEC MXS: Unable to init FEC\n");
370 static inline void tx28_init_mac(void)
373 #endif /* CONFIG_FEC_MXC */
382 static int led_state = LED_STATE_DISABLED;
384 void show_activity(int arg)
389 if (led_state == LED_STATE_DISABLED) {
391 } else if (led_state == LED_STATE_INIT) {
393 ret = gpio_request_one(TX28_LED_GPIO,
394 GPIOFLAG_OUTPUT_INIT_HIGH, "Activity");
396 led_state = LED_STATE_ON;
398 led_state = LED_STATE_DISABLED;
400 if (get_timer(last) > CONFIG_SYS_HZ) {
402 if (led_state == LED_STATE_ON) {
403 gpio_set_value(TX28_LED_GPIO, 0);
404 led_state = LED_STATE_OFF;
406 gpio_set_value(TX28_LED_GPIO, 1);
407 led_state = LED_STATE_ON;
413 static const iomux_cfg_t stk5_pads[] = {
414 /* SW controlled LED on STK5 baseboard */
415 MX28_PAD_ENET0_RXD3__GPIO_4_10 | GPIO_PAD_CTRL,
418 static const struct gpio stk5_gpios[] = {
422 vidinfo_t panel_info = {
423 /* set to max. size supported by SoC */
427 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
430 static struct fb_videomode tx28_fb_modes[] = {
432 /* Standard VGA timing */
437 .pixclock = KHZ2PICOS(25175),
444 .vmode = FB_VMODE_NONINTERLACED,
447 /* Emerging ETV570 640 x 480 display. Syncs low active,
448 * DE high active, 115.2 mm x 86.4 mm display area
449 * VGA compatible timing
455 .pixclock = KHZ2PICOS(25175),
462 .vmode = FB_VMODE_NONINTERLACED,
465 /* Emerging ET0350G0DH6 320 x 240 display.
466 * 70.08 mm x 52.56 mm display area.
472 .pixclock = KHZ2PICOS(6500),
473 .left_margin = 68 - 34,
476 .upper_margin = 18 - 3,
479 .vmode = FB_VMODE_NONINTERLACED,
482 /* Emerging ET0430G0DH6 480 x 272 display.
483 * 95.04 mm x 53.856 mm display area.
489 .pixclock = KHZ2PICOS(9000),
496 .sync = FB_SYNC_CLK_LAT_FALL,
497 .vmode = FB_VMODE_NONINTERLACED,
500 /* Emerging ET0500G0DH6 800 x 480 display.
501 * 109.6 mm x 66.4 mm display area.
507 .pixclock = KHZ2PICOS(33260),
508 .left_margin = 216 - 128,
510 .right_margin = 1056 - 800 - 216,
511 .upper_margin = 35 - 2,
513 .lower_margin = 525 - 480 - 35,
514 .vmode = FB_VMODE_NONINTERLACED,
517 /* Emerging ETQ570G0DH6 320 x 240 display.
518 * 115.2 mm x 86.4 mm display area.
524 .pixclock = KHZ2PICOS(6400),
528 .upper_margin = 16, /* 15 according to datasheet */
529 .vsync_len = 3, /* TVP -> 1>x>5 */
530 .lower_margin = 4, /* 4.5 according to datasheet */
531 .vmode = FB_VMODE_NONINTERLACED,
534 /* Emerging ET0700G0DH6 800 x 480 display.
535 * 152.4 mm x 91.44 mm display area.
541 .pixclock = KHZ2PICOS(33260),
542 .left_margin = 216 - 128,
544 .right_margin = 1056 - 800 - 216,
545 .upper_margin = 35 - 2,
547 .lower_margin = 525 - 480 - 35,
548 .vmode = FB_VMODE_NONINTERLACED,
551 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
552 .vmode = FB_VMODE_NONINTERLACED,
556 static int lcd_enabled = 1;
557 static int lcd_bl_polarity;
559 static int lcd_backlight_polarity(void)
561 return lcd_bl_polarity;
564 void lcd_enable(void)
567 * global variable from common/lcd.c
568 * Set to 0 here to prevent messages from going to LCD
569 * rather than serial console
573 karo_load_splashimage(1);
575 debug("Switching LCD on\n");
576 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
578 gpio_set_value(TX28_LCD_RST_GPIO, 1);
580 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
581 lcd_backlight_polarity());
585 void lcd_disable(void)
589 void lcd_panel_disable(void)
592 debug("Switching LCD off\n");
593 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO,
594 !lcd_backlight_polarity());
595 gpio_set_value(TX28_LCD_RST_GPIO, 0);
596 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
600 static const iomux_cfg_t stk5_lcd_pads[] = {
602 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
603 /* LCD POWER_ENABLE */
604 MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
605 /* LCD Backlight (PWM) */
606 MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
609 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
610 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
611 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
612 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
613 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
614 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
615 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
616 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
617 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
618 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
619 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
620 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
621 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
622 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
623 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
624 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
625 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
626 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
627 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
628 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
629 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
630 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
631 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
632 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
633 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
634 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
635 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
636 MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
639 static const struct gpio stk5_lcd_gpios[] = {
640 { TX28_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
641 { TX28_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
642 { TX28_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
645 void lcd_ctrl_init(void *lcdbase)
647 int color_depth = 24;
648 const char *video_mode = karo_get_vmode(getenv("video_mode"));
652 struct fb_videomode *p = tx28_fb_modes;
653 struct fb_videomode fb_mode;
654 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
657 debug("LCD disabled\n");
662 debug("Disabling LCD\n");
664 setenv("splashimage", NULL);
669 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
671 if (video_mode == NULL) {
672 debug("Disabling LCD\n");
677 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
679 debug("Using video mode from FDT\n");
681 if (fb_mode.xres > panel_info.vl_col ||
682 fb_mode.yres > panel_info.vl_row) {
683 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
684 fb_mode.xres, fb_mode.yres,
685 panel_info.vl_col, panel_info.vl_row);
691 debug("Trying compiled-in video modes\n");
692 while (p->name != NULL) {
693 if (strcmp(p->name, vm) == 0) {
694 debug("Using video mode: '%s'\n", p->name);
701 debug("Trying to decode video_mode: '%s'\n", vm);
702 while (*vm != '\0') {
703 if (*vm >= '0' && *vm <= '9') {
706 val = simple_strtoul(vm, &end, 0);
709 if (val > panel_info.vl_col)
710 val = panel_info.vl_col;
712 panel_info.vl_col = val;
714 } else if (!yres_set) {
715 if (val > panel_info.vl_row)
716 val = panel_info.vl_row;
718 panel_info.vl_row = val;
720 } else if (!bpp_set) {
730 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
731 end - vm, vm, color_depth);
734 } else if (!refresh_set) {
761 if (p->xres == 0 || p->yres == 0) {
762 printf("Invalid video mode: %s\n", getenv("video_mode"));
764 printf("Supported video modes are:");
765 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
766 printf(" %s", p->name);
771 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
772 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
773 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
777 panel_info.vl_col = p->xres;
778 panel_info.vl_row = p->yres;
780 switch (color_depth) {
782 panel_info.vl_bpix = LCD_COLOR8;
785 panel_info.vl_bpix = LCD_COLOR16;
788 panel_info.vl_bpix = LCD_COLOR32;
791 p->pixclock = KHZ2PICOS(refresh *
792 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
793 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
795 debug("Pixel clock set to %lu.%03lu MHz\n",
796 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
801 debug("Creating new display-timing node from '%s'\n",
803 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
805 printf("Failed to create new display-timing node from '%s': %d\n",
809 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
810 mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
811 ARRAY_SIZE(stk5_lcd_pads));
813 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
814 color_depth, refresh);
816 if (karo_load_splashimage(0) == 0) {
819 /* setup env variable for mxsfb display driver */
820 snprintf(vmode, sizeof(vmode),
821 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
822 p->xres, p->yres, p->left_margin, p->right_margin,
823 p->upper_margin, p->lower_margin, p->hsync_len,
824 p->vsync_len, p->sync, p->pixclock, color_depth);
825 setenv("videomode", vmode);
827 debug("Initializing LCD controller\n");
829 setenv("videomode", NULL);
831 debug("Skipping initialization of LCD controller\n");
835 #define lcd_enabled 0
836 #endif /* CONFIG_LCD */
838 static void stk5_board_init(void)
840 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
841 mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
844 static void stk5v3_board_init(void)
846 led_state = LED_STATE_INIT;
850 static void stk5v5_board_init(void)
854 /* init flexcan transceiver enable GPIO */
855 gpio_request_one(STK5_CAN_XCVR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH,
856 "Flexcan Transceiver");
857 mxs_iomux_setup_pad(STK5_CAN_XCVR_PAD);
860 int board_late_init(void)
863 const char *baseboard;
868 setenv_ulong("safeboot", 1);
872 baseboard = getenv("baseboard");
876 printf("Baseboard: %s\n", baseboard);
878 if (strncmp(baseboard, "stk5", 4) == 0) {
879 if ((strlen(baseboard) == 4) ||
880 strcmp(baseboard, "stk5-v3") == 0) {
882 } else if (strcmp(baseboard, "stk5-v5") == 0) {
883 const char *otg_mode = getenv("otg_mode");
885 if (otg_mode && strcmp(otg_mode, "host") == 0) {
886 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
887 otg_mode, baseboard);
888 setenv("otg_mode", "none");
892 printf("WARNING: Unsupported STK5 board rev.: %s\n",
896 printf("WARNING: Unsupported baseboard: '%s'\n",
908 #define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
909 RTC_PERSISTENT0_ALARM_WAKE | \
910 RTC_PERSISTENT0_THERMAL_RESET)
912 static void thermal_init(void)
914 struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
915 struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
917 writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
918 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
919 &power_regs->hw_power_thermal);
921 writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
922 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
923 &clkctrl_regs->hw_clkctrl_reset);
928 struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
929 u32 pwr_sts = readl(&power_regs->hw_power_sts);
930 u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
931 const char *dlm = "";
933 printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
934 CONFIG_SYS_SDRAM_SIZE / SZ_128M +
935 CONFIG_SYS_NAND_BLOCKS / 2048 * 2);
937 printf("POWERUP Source: ");
938 if (pwrup_src & (3 << 0)) {
939 printf("%sPSWITCH %s voltage", dlm,
940 pwrup_src & (1 << 1) ? "HIGH" : "MID");
943 if (pwrup_src & (1 << 4)) {
944 printf("%sRTC", dlm);
947 if (pwrup_src & (1 << 5)) {
953 if (boot_cause & BOOT_CAUSE_MASK) {
955 printf("Last boot cause: ");
956 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
957 printf("%sEXTERNAL", dlm);
960 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
961 printf("%sTHERMAL", dlm);
966 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
967 printf("%sALARM WAKE", dlm);
973 while (pwr_sts & POWER_STS_THERMAL_WARNING) {
974 static int first = 1;
977 printf("CPU too hot to boot\n");
982 pwr_sts = readl(&power_regs->hw_power_sts);
985 if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
991 #if defined(CONFIG_OF_BOARD_SETUP)
992 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
993 #include <jffs2/jffs2.h>
994 #include <mtd_node.h>
995 static struct node_info tx28_nand_nodes[] = {
996 { "fsl,imx28-gpmi-nand", MTD_DEV_TYPE_NAND, },
999 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1002 static const char *tx28_touchpanels[] = {
1008 int ft_board_setup(void *blob, bd_t *bd)
1010 const char *baseboard = getenv("baseboard");
1011 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1012 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1015 ret = fdt_increase_size(blob, 4096);
1017 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1020 #ifdef CONFIG_TX28_S
1021 /* TX28-41xx (aka TX28S) has no external RTC
1022 * and no I2C GPIO extender
1024 karo_fdt_remove_node(blob, "ds1339");
1025 karo_fdt_remove_node(blob, "gpio5");
1028 karo_fdt_enable_node(blob, "stk5led", 0);
1030 fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
1032 karo_fdt_fixup_touchpanel(blob, tx28_touchpanels,
1033 ARRAY_SIZE(tx28_touchpanels));
1034 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1035 karo_fdt_fixup_flexcan(blob, stk5_v5);
1036 karo_fdt_update_fb_mode(blob, video_mode);
1040 #endif /* CONFIG_OF_BOARD_SETUP */