2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <fdt_support.h>
31 #include <imx_ssp_mmc.h>
32 #include <linux/list.h>
36 #include <asm/arch/iomux-mx28.h>
37 #include <asm/arch/clock.h>
38 #include <asm/arch/mxsfb.h>
39 #include <asm/arch/imx-regs.h>
40 #include <asm/arch/sys_proto.h>
42 #include "../common/karo.h"
44 DECLARE_GLOBAL_DATA_PTR;
46 #define MXS_GPIO_NR(p, o) (((p) << 5) | (o))
48 #define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31
49 #define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30
50 #define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
52 #define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27
53 #define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20
54 #define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
55 #define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19
56 #define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18
58 #define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10
60 static const struct gpio tx28_gpios[] = {
61 { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
62 { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
63 { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
64 { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
65 { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
68 static const iomux_cfg_t tx28_pads[] = {
70 #if CONFIG_CONS_INDEX == 0
71 MX28_PAD_AUART0_RX__DUART_CTS,
72 MX28_PAD_AUART0_TX__DUART_RTS,
73 MX28_PAD_AUART0_CTS__DUART_RX,
74 MX28_PAD_AUART0_RTS__DUART_TX,
75 #elif CONFIG_CONS_INDEX == 1
76 MX28_PAD_AUART1_RX__AUART1_RX,
77 MX28_PAD_AUART1_TX__AUART1_TX,
78 MX28_PAD_AUART1_CTS__AUART1_CTS,
79 MX28_PAD_AUART1_RTS__AUART1_RTS,
80 #elif CONFIG_CONS_INDEX == 2
81 MX28_PAD_AUART3_RX__AUART3_RX,
82 MX28_PAD_AUART3_TX__AUART3_TX,
83 MX28_PAD_AUART3_CTS__AUART3_CTS,
84 MX28_PAD_AUART3_RTS__AUART3_RTS,
86 /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
87 MX28_PAD_I2C0_SCL__I2C0_SCL,
88 MX28_PAD_I2C0_SDA__I2C0_SDA,
91 MX28_PAD_SPDIF__GPIO_3_27,
92 MX28_PAD_JTAG_RTCK__GPIO_4_20,
94 /* USBOTG VBUSEN, OC, ID */
95 MX28_PAD_GPMI_CE2N__GPIO_0_18,
96 MX28_PAD_GPMI_CE3N__GPIO_0_19,
97 MX28_PAD_PWM2__GPIO_3_18,
104 /* provide at least _some_ sort of randomness */
105 #define MAX_LOOPS 100
109 static inline void random_init(void)
111 struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE;
115 for (i = 0; i < MAX_LOOPS; i++) {
116 unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds);
118 seed = get_timer(usec + random + seed);
124 #define RTC_PERSISTENT0_CLK32_MASK (RTC_PERSISTENT0_CLOCKSOURCE | \
125 RTC_PERSISTENT0_XTAL32KHZ_PWRUP)
126 static u32 boot_cause __attribute__((section("data")));
128 int board_early_init_f(void)
130 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
136 /* IO0 clock at 480MHz */
137 mx28_set_ioclk(MXC_IOCLK0, 480000);
138 /* IO1 clock at 480MHz */
139 mx28_set_ioclk(MXC_IOCLK1, 480000);
141 /* SSP0 clock at 96MHz */
142 mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
143 /* SSP2 clock at 96MHz */
144 mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
146 gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
147 mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
149 while ((rtc_stat = readl(&rtc_regs->hw_rtc_stat)) &
150 RTC_STAT_STALE_REGS_PERSISTENT0) {
155 boot_cause = readl(&rtc_regs->hw_rtc_persistent0);
156 if ((boot_cause & RTC_PERSISTENT0_CLK32_MASK) !=
157 RTC_PERSISTENT0_CLK32_MASK) {
158 if (boot_cause & RTC_PERSISTENT0_CLOCKSOURCE)
160 writel(RTC_PERSISTENT0_CLK32_MASK,
161 &rtc_regs->hw_rtc_persistent0_set);
166 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
172 /* Address of boot parameters */
173 #ifdef CONFIG_OF_LIBFDT
174 gd->bd->bi_arch_number = -1;
176 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
182 return mxs_dram_init();
185 #ifdef CONFIG_CMD_MMC
186 static int tx28_mmc_wp(int dev_no)
191 int board_mmc_init(bd_t *bis)
193 return mxsmmc_initialize(bis, 0, tx28_mmc_wp);
195 #endif /* CONFIG_CMD_MMC */
197 #ifdef CONFIG_FEC_MXC
198 #ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
200 #ifdef CONFIG_FEC_MXC_MULTI
201 #define FEC_MAX_IDX 1
203 #define FEC_MAX_IDX 0
206 static int fec_get_mac_addr(int index)
210 struct mxs_ocotp_regs *ocotp_regs =
211 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
212 u32 *cust = &ocotp_regs->hw_ocotp_cust0;
214 char env_name[] = "eth.addr";
216 if (index < 0 || index > FEC_MAX_IDX)
219 /* set this bit to open the OTP banks for reading */
220 writel(OCOTP_CTRL_RD_BANK_OPEN,
221 &ocotp_regs->hw_ocotp_ctrl_set);
223 /* wait until OTP contents are readable */
224 while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
230 val1 = readl(&cust[index * 8]);
231 val2 = readl(&cust[index * 8 + 4]);
232 if ((val1 | val2) == 0)
234 snprintf(mac, sizeof(mac), "%02x:%02x:%02x:%02x:%02x:%02x",
235 (val1 >> 24) & 0xFF, (val1 >> 16) & 0xFF,
236 (val1 >> 8) & 0xFF, (val1 >> 0) & 0xFF,
237 (val2 >> 24) & 0xFF, (val2 >> 16) & 0xFF);
239 snprintf(env_name, sizeof(env_name), "ethaddr");
241 snprintf(env_name, sizeof(env_name), "eth%daddr", index);
243 setenv(env_name, mac);
246 #endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
248 static const iomux_cfg_t tx28_fec_pads[] = {
249 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
250 MX28_PAD_ENET0_RXD0__ENET0_RXD0,
251 MX28_PAD_ENET0_RXD1__ENET0_RXD1,
254 int board_eth_init(bd_t *bis)
258 /* Reset the external phy */
259 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
261 /* Power on the external phy */
262 gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
264 /* Pull strap pins to high */
265 gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
266 gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
267 gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
268 gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
271 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
274 mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
276 ret = cpu_eth_init(bis);
278 printf("cpu_eth_init() failed: %d\n", ret);
282 ret = fec_get_mac_addr(0);
284 printf("Failed to read FEC0 MAC address from OCOTP\n");
287 #ifdef CONFIG_FEC_MXC_MULTI
288 if (getenv("ethaddr")) {
289 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
291 printf("FEC MXS: Unable to init FEC0\n");
296 ret = fec_get_mac_addr(1);
298 printf("Failed to read FEC1 MAC address from OCOTP\n");
301 if (getenv("eth1addr")) {
302 ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
304 printf("FEC MXS: Unable to init FEC1\n");
310 if (getenv("ethaddr")) {
311 ret = fecmxc_initialize(bis);
316 #endif /* CONFIG_FEC_MXC */
324 void show_activity(int arg)
326 static int led_state = LED_STATE_INIT;
329 if (led_state == LED_STATE_INIT) {
331 gpio_set_value(TX28_LED_GPIO, 1);
332 led_state = LED_STATE_ON;
334 if (get_timer(last) > CONFIG_SYS_HZ) {
336 if (led_state == LED_STATE_ON) {
337 gpio_set_value(TX28_LED_GPIO, 0);
339 gpio_set_value(TX28_LED_GPIO, 1);
341 led_state = 1 - led_state;
346 static const iomux_cfg_t stk5_pads[] = {
347 /* SW controlled LED on STK5 baseboard */
348 MX28_PAD_ENET0_RXD3__GPIO_4_10,
351 static const struct gpio stk5_gpios[] = {
355 static struct fb_videomode tx28_fb_modes[] = {
357 /* Standard VGA timing */
362 .pixclock = KHZ2PICOS(25175),
369 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
370 .vmode = FB_VMODE_NONINTERLACED,
373 /* Emerging ETV570 640 x 480 display. Syncs low active,
374 * DE high active, 115.2 mm x 86.4 mm display area
375 * VGA compatible timing
381 .pixclock = KHZ2PICOS(25175),
388 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
389 .vmode = FB_VMODE_NONINTERLACED,
392 /* Emerging ET0350G0DH6 320 x 240 display.
393 * 70.08 mm x 52.56 mm display area.
399 .pixclock = KHZ2PICOS(6500),
400 .left_margin = 68 - 34,
403 .upper_margin = 18 - 3,
406 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
407 .vmode = FB_VMODE_NONINTERLACED,
410 /* Emerging ET0430G0DH6 480 x 272 display.
411 * 95.04 mm x 53.856 mm display area.
417 .pixclock = KHZ2PICOS(9000),
424 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
425 .vmode = FB_VMODE_NONINTERLACED,
428 /* Emerging ET0500G0DH6 800 x 480 display.
429 * 109.6 mm x 66.4 mm display area.
435 .pixclock = KHZ2PICOS(33260),
436 .left_margin = 216 - 128,
438 .right_margin = 1056 - 800 - 216,
439 .upper_margin = 35 - 2,
441 .lower_margin = 525 - 480 - 35,
442 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
443 .vmode = FB_VMODE_NONINTERLACED,
446 /* Emerging ETQ570G0DH6 320 x 240 display.
447 * 115.2 mm x 86.4 mm display area.
453 .pixclock = KHZ2PICOS(6400),
457 .upper_margin = 16, /* 15 according to datasheet */
458 .vsync_len = 3, /* TVP -> 1>x>5 */
459 .lower_margin = 4, /* 4.5 according to datasheet */
460 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
461 .vmode = FB_VMODE_NONINTERLACED,
464 /* Emerging ET0700G0DH6 800 x 480 display.
465 * 152.4 mm x 91.44 mm display area.
471 .pixclock = KHZ2PICOS(33260),
472 .left_margin = 216 - 128,
474 .right_margin = 1056 - 800 - 216,
475 .upper_margin = 35 - 2,
477 .lower_margin = 525 - 480 - 35,
478 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
479 .vmode = FB_VMODE_NONINTERLACED,
482 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
483 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
484 .vmode = FB_VMODE_NONINTERLACED,
488 static int lcd_enabled = 1;
490 void lcd_enable(void)
493 * global variable from common/lcd.c
494 * Set to 0 here to prevent messages from going to LCD
495 * rather than serial console
499 karo_load_splashimage(1);
501 debug("Switching LCD on\n");
502 gpio_set_value(TX28_LCD_PWR_GPIO, 1);
504 gpio_set_value(TX28_LCD_RST_GPIO, 1);
506 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0);
510 void lcd_disable(void)
515 void lcd_panel_disable(void)
518 debug("Switching LCD off\n");
519 gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1);
520 gpio_set_value(TX28_LCD_RST_GPIO, 0);
521 gpio_set_value(TX28_LCD_PWR_GPIO, 0);
525 static const iomux_cfg_t stk5_lcd_pads[] = {
527 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
528 /* LCD POWER_ENABLE */
529 MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
530 /* LCD Backlight (PWM) */
531 MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
534 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
535 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
536 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
537 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
538 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
539 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
540 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
541 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
542 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
543 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
544 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
545 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
546 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
547 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
548 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
549 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
550 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
551 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
552 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
553 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
554 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
555 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
556 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
557 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
558 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
559 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
560 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
561 MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
562 MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
563 MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
564 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
567 static const struct gpio stk5_lcd_gpios[] = {
568 { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
569 { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
570 { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
573 extern void video_hw_init(void *lcdbase);
575 void lcd_ctrl_init(void *lcdbase)
577 int color_depth = 24;
581 struct fb_videomode *p = tx28_fb_modes;
582 struct fb_videomode fb_mode;
583 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
586 debug("LCD disabled\n");
591 debug("Disabling LCD\n");
598 vm = getenv("video_mode");
600 debug("Disabling LCD\n");
604 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
606 debug("Using video mode from FDT\n");
610 debug("Trying compiled-in video modes\n");
611 while (p->name != NULL) {
612 if (strcmp(p->name, vm) == 0) {
613 debug("Using video mode: '%s'\n", p->name);
620 debug("Trying to decode video_mode: '%s'\n", vm);
621 while (*vm != '\0') {
622 if (*vm >= '0' && *vm <= '9') {
625 val = simple_strtoul(vm, &end, 0);
628 if (val > panel_info.vl_col)
629 val = panel_info.vl_col;
632 } else if (!yres_set) {
633 if (val > panel_info.vl_row)
634 val = panel_info.vl_row;
637 } else if (!bpp_set) {
647 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
648 end - vm, vm, color_depth);
651 } else if (!refresh_set) {
678 if (p->xres == 0 || p->yres == 0) {
679 printf("Invalid video mode: %s\n", getenv("video_mode"));
681 printf("Supported video modes are:");
682 for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
683 printf(" %s", p->name);
688 p->pixclock = KHZ2PICOS(refresh *
689 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
690 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
692 debug("Pixel clock set to %lu.%03lu MHz\n",
693 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
695 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
696 mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
697 ARRAY_SIZE(stk5_lcd_pads));
699 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
700 color_depth, refresh);
702 if (karo_load_splashimage(0) == 0) {
703 debug("Initializing LCD controller\n");
704 mxsfb_init(p, PIX_FMT_RGB24, color_depth);
705 video_hw_init(lcdbase);
707 debug("Skipping initialization of LCD controller\n");
711 #define lcd_enabled 0
712 #endif /* CONFIG_LCD */
714 static void stk5_board_init(void)
716 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
717 mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
720 static void stk5v3_board_init(void)
725 static void stk5v5_board_init(void)
729 /* init flexcan transceiver enable GPIO */
730 gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
731 "Flexcan Transceiver");
732 mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
735 int board_late_init(void)
737 const char *baseboard;
741 baseboard = getenv("baseboard");
745 if (strncmp(baseboard, "stk5", 4) == 0) {
746 printf("Baseboard: %s\n", baseboard);
747 if ((strlen(baseboard) == 4) ||
748 strcmp(baseboard, "stk5-v3") == 0) {
750 } else if (strcmp(baseboard, "stk5-v5") == 0) {
751 const char *otg_mode = getenv("otg_mode");
753 if (otg_mode && strcmp(otg_mode, "host") == 0) {
754 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
755 otg_mode, baseboard);
756 setenv("otg_mode", "none");
760 printf("WARNING: Unsupported STK5 board rev.: %s\n",
764 printf("WARNING: Unsupported baseboard: '%s'\n",
772 #define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
773 RTC_PERSISTENT0_ALARM_WAKE | \
774 RTC_PERSISTENT0_THERMAL_RESET)
776 static void thermal_init(void)
778 struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
779 struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE;
781 writel(POWER_THERMAL_LOW_POWER | POWER_THERMAL_OFFSET_ADJ_ENABLE |
782 POWER_THERMAL_OFFSET_ADJ_OFFSET(3),
783 &power_regs->hw_power_thermal);
785 writel(CLKCTRL_RESET_EXTERNAL_RESET_ENABLE |
786 CLKCTRL_RESET_THERMAL_RESET_ENABLE,
787 &clkctrl_regs->hw_clkctrl_reset);
792 struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
793 u32 pwr_sts = readl(&power_regs->hw_power_sts);
794 u32 pwrup_src = (pwr_sts >> 24) & 0x3f;
795 const char *dlm = "";
797 printf("Board: Ka-Ro TX28-4%sx%d\n", TX28_MOD_SUFFIX,
798 CONFIG_SDRAM_SIZE / SZ_128M);
800 printf("POWERUP Source: ");
801 if (pwrup_src & (3 << 0)) {
802 printf("%sPSWITCH %s voltage", dlm,
803 pwrup_src & (1 << 1) ? "HIGH" : "MID");
806 if (pwrup_src & (1 << 4)) {
807 printf("%sRTC", dlm);
810 if (pwrup_src & (1 << 5)) {
816 if (boot_cause & BOOT_CAUSE_MASK) {
818 printf("Last boot cause: ");
819 if (boot_cause & RTC_PERSISTENT0_EXTERNAL_RESET) {
820 printf("%sEXTERNAL", dlm);
823 if (boot_cause & RTC_PERSISTENT0_THERMAL_RESET) {
824 printf("%sTHERMAL", dlm);
829 if (boot_cause & RTC_PERSISTENT0_ALARM_WAKE) {
830 printf("%sALARM WAKE", dlm);
836 while (pwr_sts & POWER_STS_THERMAL_WARNING) {
837 static int first = 1;
840 printf("CPU too hot to boot\n");
845 pwr_sts = readl(&power_regs->hw_power_sts);
848 if (!(boot_cause & RTC_PERSISTENT0_THERMAL_RESET))
854 #if defined(CONFIG_OF_BOARD_SETUP)
855 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
856 #include <jffs2/jffs2.h>
857 #include <mtd_node.h>
858 struct node_info tx28_nand_nodes[] = {
859 { "gpmi-nand", MTD_DEV_TYPE_NAND, },
862 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
865 static void tx28_fixup_flexcan(void *blob)
867 karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80032000, "transceiver-switch");
868 karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80034000, "transceiver-switch");
871 static void tx28_fixup_fec(void *blob)
873 karo_fdt_enable_node(blob, "ethernet1", 0);
876 void ft_board_setup(void *blob, bd_t *bd)
878 const char *baseboard = getenv("baseboard");
881 /* TX28-41xx (aka TX28S) has no external RTC
882 * and no I2C GPIO extender
884 karo_fdt_remove_node(blob, "ds1339");
885 karo_fdt_remove_node(blob, "gpio5");
887 if (baseboard != NULL && strcmp(baseboard, "stk5-v5") == 0) {
888 karo_fdt_remove_node(blob, "stk5led");
890 tx28_fixup_flexcan(blob);
891 tx28_fixup_fec(blob);
894 if (baseboard != NULL && strcmp(baseboard, "stk5-v3") == 0) {
895 const char *otg_mode = getenv("otg_mode");
897 if (otg_mode && (strcmp(otg_mode, "device") == 0 ||
898 strcmp(otg_mode, "gadget") == 0))
899 karo_fdt_enable_node(blob, "can1", 0);
902 fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
903 fdt_fixup_ethernet(blob);
905 karo_fdt_fixup_touchpanel(blob);
906 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
907 karo_fdt_update_fb_mode(blob, getenv("video_mode"));