2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
23 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
34 #include <asm/arch/iomux-mx51.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
38 #include <asm/arch/sys_proto.h>
40 #include "../common/karo.h"
42 #define TX51_FEC_RST_GPIO IMX_GPIO_NR(2, 14)
43 #define TX51_FEC_PWR_GPIO IMX_GPIO_NR(1, 3)
44 #define TX51_FEC_INT_GPIO IMX_GPIO_NR(3, 18)
45 #define TX51_LED_GPIO IMX_GPIO_NR(4, 10)
47 #define TX51_LCD_PWR_GPIO IMX_GPIO_NR(4, 14)
48 #define TX51_LCD_RST_GPIO IMX_GPIO_NR(4, 13)
49 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
51 #define TX51_RESET_OUT_GPIO IMX_GPIO_NR(2, 15)
53 DECLARE_GLOBAL_DATA_PTR;
55 #define IOMUX_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
57 #define FEC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
59 #define FEC_PAD_CTRL2 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
60 #define GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
62 static iomux_v3_cfg_t tx51_pads[] = {
63 /* NAND flash pads are set up in lowlevel_init.S */
66 MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
69 #if CONFIG_MXC_UART_BASE == UART1_BASE
70 MX51_PAD_UART1_RXD__UART1_RXD,
71 MX51_PAD_UART1_TXD__UART1_TXD,
72 MX51_PAD_UART1_RTS__UART1_RTS,
73 MX51_PAD_UART1_CTS__UART1_CTS,
75 #if CONFIG_MXC_UART_BASE == UART2_BASE
76 MX51_PAD_UART2_RXD__UART2_RXD,
77 MX51_PAD_UART2_TXD__UART2_TXD,
78 MX51_PAD_EIM_D26__UART2_RTS,
79 MX51_PAD_EIM_D25__UART2_CTS,
81 #if CONFIG_MXC_UART_BASE == UART3_BASE
82 MX51_PAD_UART3_RXD__UART3_RXD,
83 MX51_PAD_UART3_TXD__UART3_TXD,
84 MX51_PAD_EIM_D18__UART3_RTS,
85 MX51_PAD_EIM_D17__UART3_CTS,
88 MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
89 MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
91 /* FEC PHY GPIO functions */
92 MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL, /* PHY POWER */
93 MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL, /* PHY RESET */
94 MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
97 MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
98 MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
99 MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
100 MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
101 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
102 MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
103 MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
104 MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
105 MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
106 MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
108 /* strap pins for PHY configuration */
109 MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
110 MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL, /* RXD0/Mode0 */
111 MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL, /* RXD1/Mode1 */
112 MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL, /* RXD2/Mode2 */
113 MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL, /* RXD3/nINTSEL */
114 MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
115 MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL, /* CRS/PHYAD4 */
117 /* unusable pins on TX51 */
118 MX51_PAD_GPIO1_0__GPIO1_0,
119 MX51_PAD_GPIO1_1__GPIO1_1,
122 static const struct gpio tx51_gpios[] = {
124 { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
126 /* FEC PHY control GPIOs */
127 { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
128 { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
129 { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
131 /* FEC PHY strap pins */
132 { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
133 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
134 { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
135 { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
136 { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
137 { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
138 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
140 /* module internal I2C bus */
141 { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
142 { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
144 /* Unconnected pins */
145 { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
146 { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
152 /* placed in section '.data' to prevent overwriting relocation info
155 static u32 wrsr __attribute__((section(".data")));
157 #define WRSR_POR (1 << 4)
158 #define WRSR_TOUT (1 << 1)
159 #define WRSR_SFTW (1 << 0)
161 static void print_reset_cause(void)
163 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
164 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
168 printf("Reset cause: ");
170 srsr = readl(&src_regs->srsr);
171 wrsr = readw(wdt_base + 4);
173 if (wrsr & WRSR_POR) {
174 printf("%sPOR", dlm);
177 if (srsr & 0x00004) {
178 printf("%sCSU", dlm);
181 if (srsr & 0x00008) {
182 printf("%sIPP USER", dlm);
185 if (srsr & 0x00010) {
186 if (wrsr & WRSR_SFTW) {
187 printf("%sSOFT", dlm);
190 if (wrsr & WRSR_TOUT) {
191 printf("%sWDOG", dlm);
195 if (srsr & 0x00020) {
196 printf("%sJTAG HIGH-Z", dlm);
199 if (srsr & 0x00040) {
200 printf("%sJTAG SW", dlm);
203 if (srsr & 0x10000) {
204 printf("%sWARM BOOT", dlm);
213 static void tx51_print_cpuinfo(void)
217 cpurev = get_cpu_rev();
219 printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n",
220 (cpurev & 0x000F0) >> 4,
221 (cpurev & 0x0000F) >> 0,
222 mxc_get_clock(MXC_ARM_CLK) / 1000000);
227 int board_early_init_f(void)
229 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
231 gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
232 imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
234 writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
235 writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
237 writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
238 writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
239 writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
240 writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
241 writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
243 writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
244 writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
246 writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
247 writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
248 writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
249 writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
250 writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
252 writel(0xffcffffc, &ccm_regs->CCGR0);
253 writel(0x003fffff, &ccm_regs->CCGR1);
254 writel(0x030c003c, &ccm_regs->CCGR2);
255 writel(0x000000ff, &ccm_regs->CCGR3);
256 writel(0x00000000, &ccm_regs->CCGR4);
257 writel(0x003fc003, &ccm_regs->CCGR5);
258 writel(0x00000000, &ccm_regs->CCGR6);
259 writel(0x00000000, &ccm_regs->cmeor);
260 #ifdef CONFIG_CMD_BOOTCE
261 /* WinCE fails to enable these clocks */
262 writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
263 writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
264 writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
271 /* Address of boot parameters */
272 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
280 /* dram_init must store complete ramsize in gd->ram_size */
281 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
284 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
285 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
287 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
288 CONFIG_SYS_SDRAM_CLK, ret);
290 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
291 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
292 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
293 CONFIG_SYS_SDRAM_CLK);
297 void dram_init_banksize(void)
299 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
300 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
302 #if CONFIG_NR_DRAM_BANKS > 1
303 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
304 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
309 #ifdef CONFIG_CMD_MMC
310 static const iomux_v3_cfg_t mmc0_pads[] = {
311 MX51_PAD_SD1_CMD__SD1_CMD,
312 MX51_PAD_SD1_CLK__SD1_CLK,
313 MX51_PAD_SD1_DATA0__SD1_DATA0,
314 MX51_PAD_SD1_DATA1__SD1_DATA1,
315 MX51_PAD_SD1_DATA2__SD1_DATA2,
316 MX51_PAD_SD1_DATA3__SD1_DATA3,
318 MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
321 static const iomux_v3_cfg_t mmc1_pads[] = {
322 MX51_PAD_SD2_CMD__SD2_CMD,
323 MX51_PAD_SD2_CLK__SD2_CLK,
324 MX51_PAD_SD2_DATA0__SD2_DATA0,
325 MX51_PAD_SD2_DATA1__SD2_DATA1,
326 MX51_PAD_SD2_DATA2__SD2_DATA2,
327 MX51_PAD_SD2_DATA3__SD2_DATA3,
329 MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
332 static struct tx51_esdhc_cfg {
333 const iomux_v3_cfg_t *pads;
335 struct fsl_esdhc_cfg cfg;
337 } tx51_esdhc_cfg[] = {
340 .num_pads = ARRAY_SIZE(mmc0_pads),
342 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
345 .cd_gpio = IMX_GPIO_NR(3, 8),
349 .num_pads = ARRAY_SIZE(mmc1_pads),
351 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
354 .cd_gpio = IMX_GPIO_NR(3, 6),
358 #define to_tx51_esdhc_cfg(p) container_of(p, struct tx51_esdhc_cfg, cfg)
360 int board_mmc_getcd(struct mmc *mmc)
362 struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
364 if (cfg->cd_gpio < 0)
367 debug("SD card %d is %spresent\n",
368 cfg - tx51_esdhc_cfg,
369 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
370 return !gpio_get_value(cfg->cd_gpio);
373 int board_mmc_init(bd_t *bis)
377 for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
379 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
382 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
385 imx_iomux_v3_setup_multiple_pads(cfg->pads,
387 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
389 fsl_esdhc_initialize(bis, &cfg->cfg);
391 ret = gpio_request_one(cfg->cd_gpio,
392 GPIOF_INPUT, "MMC CD");
394 printf("Error %d requesting GPIO%d_%d\n",
395 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
399 mmc = find_mmc_device(i);
402 if (board_mmc_getcd(mmc) > 0)
407 #endif /* CONFIG_CMD_MMC */
409 #ifdef CONFIG_FEC_MXC
415 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
418 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
419 struct fuse_bank *bank = &iim->bank[1];
420 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
425 for (i = 0; i < ETH_ALEN; i++)
426 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
429 static iomux_v3_cfg_t tx51_fec_pads[] = {
430 /* reconfigure strap pins for FEC function */
431 MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
432 MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
433 MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
434 MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
435 MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
436 MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
437 MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
440 /* take bit 4 of PHY address from configured PHY address or
441 * set it to 0 if PHYADDR is -1 (probe for PHY)
443 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
445 static struct gpio tx51_fec_gpios[] = {
446 { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
447 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
448 { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
449 { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
450 { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
452 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
454 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
458 int board_eth_init(bd_t *bis)
461 unsigned char mac[ETH_ALEN];
463 /* Power up the external phy and assert strap options */
464 gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
466 /* delay at least 21ms for the PHY internal POR signal to deassert */
469 /* Deassert RESET to the external phy */
470 gpio_set_value(TX51_FEC_RST_GPIO, 1);
472 /* Without this delay the PHY won't work, though nothing in
473 * the datasheets suggests that it should be necessary!
476 imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
477 ARRAY_SIZE(tx51_fec_pads));
479 ret = cpu_eth_init(bis);
481 printf("cpu_eth_init() failed: %d\n", ret);
485 imx_get_mac_from_fuse(0, mac);
486 eth_setenv_enetaddr("ethaddr", mac);
487 printf("MAC addr from fuse: %pM\n", mac);
491 #endif /* CONFIG_FEC_MXC */
499 void show_activity(int arg)
501 static int led_state = LED_STATE_INIT;
504 if (led_state == LED_STATE_INIT) {
506 gpio_set_value(TX51_LED_GPIO, 1);
507 led_state = LED_STATE_ON;
509 if (get_timer(last) > CONFIG_SYS_HZ) {
511 if (led_state == LED_STATE_ON) {
512 gpio_set_value(TX51_LED_GPIO, 0);
514 gpio_set_value(TX51_LED_GPIO, 1);
516 led_state = 1 - led_state;
521 static const iomux_v3_cfg_t stk5_pads[] = {
522 /* SW controlled LED on STK5 baseboard */
523 MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
526 MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
528 MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
529 /* USB PHY clock enable */
530 MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
531 /* USBH1 VBUS enable */
532 MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
534 MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
537 static const struct gpio stk5_gpios[] = {
538 { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
540 { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
541 { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
542 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
543 { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
544 { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
548 static ushort tx51_cmap[256];
549 vidinfo_t panel_info = {
550 /* set to max. size supported by SoC */
554 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
558 static struct fb_videomode tx51_fb_modes[] = {
560 /* Standard VGA timing */
565 .pixclock = KHZ2PICOS(25175),
572 .sync = FB_SYNC_CLK_LAT_FALL,
575 /* Emerging ETV570 640 x 480 display. Syncs low active,
576 * DE high active, 115.2 mm x 86.4 mm display area
577 * VGA compatible timing
583 .pixclock = KHZ2PICOS(25175),
590 .sync = FB_SYNC_CLK_LAT_FALL,
593 /* Emerging ET0350G0DH6 320 x 240 display.
594 * 70.08 mm x 52.56 mm display area.
600 .pixclock = KHZ2PICOS(6500),
601 .left_margin = 68 - 34,
604 .upper_margin = 18 - 3,
607 .sync = FB_SYNC_CLK_LAT_FALL,
610 /* Emerging ET0430G0DH6 480 x 272 display.
611 * 95.04 mm x 53.856 mm display area.
617 .pixclock = KHZ2PICOS(9000),
624 .sync = FB_SYNC_CLK_LAT_FALL,
627 /* Emerging ET0500G0DH6 800 x 480 display.
628 * 109.6 mm x 66.4 mm display area.
634 .pixclock = KHZ2PICOS(33260),
635 .left_margin = 216 - 128,
637 .right_margin = 1056 - 800 - 216,
638 .upper_margin = 35 - 2,
640 .lower_margin = 525 - 480 - 35,
641 .sync = FB_SYNC_CLK_LAT_FALL,
644 /* Emerging ETQ570G0DH6 320 x 240 display.
645 * 115.2 mm x 86.4 mm display area.
651 .pixclock = KHZ2PICOS(6400),
655 .upper_margin = 16, /* 15 according to datasheet */
656 .vsync_len = 3, /* TVP -> 1>x>5 */
657 .lower_margin = 4, /* 4.5 according to datasheet */
658 .sync = FB_SYNC_CLK_LAT_FALL,
661 /* Emerging ET0700G0DH6 800 x 480 display.
662 * 152.4 mm x 91.44 mm display area.
668 .pixclock = KHZ2PICOS(33260),
669 .left_margin = 216 - 128,
671 .right_margin = 1056 - 800 - 216,
672 .upper_margin = 35 - 2,
674 .lower_margin = 525 - 480 - 35,
675 .sync = FB_SYNC_CLK_LAT_FALL,
678 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
686 .sync = FB_SYNC_CLK_LAT_FALL,
690 static int lcd_enabled = 1;
692 void lcd_enable(void)
695 * global variable from common/lcd.c
696 * Set to 0 here to prevent messages from going to LCD
697 * rather than serial console
701 karo_load_splashimage(1);
703 debug("Switching LCD on\n");
704 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
706 gpio_set_value(TX51_LCD_RST_GPIO, 1);
708 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0);
712 void lcd_disable(void)
714 printf("Disabling LCD\n");
717 void lcd_panel_disable(void)
720 debug("Switching LCD off\n");
721 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 1);
722 gpio_set_value(TX51_LCD_RST_GPIO, 0);
723 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
727 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
729 MX51_PAD_CSI2_VSYNC__GPIO4_13,
730 /* LCD POWER_ENABLE */
731 MX51_PAD_CSI2_HSYNC__GPIO4_14,
732 /* LCD Backlight (PWM) */
733 MX51_PAD_GPIO1_2__GPIO1_2,
736 MX51_PAD_DISP1_DAT0__DISP1_DAT0,
737 MX51_PAD_DISP1_DAT1__DISP1_DAT1,
738 MX51_PAD_DISP1_DAT2__DISP1_DAT2,
739 MX51_PAD_DISP1_DAT3__DISP1_DAT3,
740 MX51_PAD_DISP1_DAT4__DISP1_DAT4,
741 MX51_PAD_DISP1_DAT5__DISP1_DAT5,
742 MX51_PAD_DISP1_DAT6__DISP1_DAT6,
743 MX51_PAD_DISP1_DAT7__DISP1_DAT7,
744 MX51_PAD_DISP1_DAT8__DISP1_DAT8,
745 MX51_PAD_DISP1_DAT9__DISP1_DAT9,
746 MX51_PAD_DISP1_DAT10__DISP1_DAT10,
747 MX51_PAD_DISP1_DAT11__DISP1_DAT11,
748 MX51_PAD_DISP1_DAT12__DISP1_DAT12,
749 MX51_PAD_DISP1_DAT13__DISP1_DAT13,
750 MX51_PAD_DISP1_DAT14__DISP1_DAT14,
751 MX51_PAD_DISP1_DAT15__DISP1_DAT15,
752 MX51_PAD_DISP1_DAT16__DISP1_DAT16,
753 MX51_PAD_DISP1_DAT17__DISP1_DAT17,
754 MX51_PAD_DISP1_DAT18__DISP1_DAT18,
755 MX51_PAD_DISP1_DAT19__DISP1_DAT19,
756 MX51_PAD_DISP1_DAT20__DISP1_DAT20,
757 MX51_PAD_DISP1_DAT21__DISP1_DAT21,
758 MX51_PAD_DISP1_DAT22__DISP1_DAT22,
759 MX51_PAD_DISP1_DAT23__DISP1_DAT23,
760 MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
761 MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
764 static const struct gpio stk5_lcd_gpios[] = {
765 { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
766 { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
767 { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
770 void lcd_ctrl_init(void *lcdbase)
772 int color_depth = 24;
776 struct fb_videomode *p = &tx51_fb_modes[0];
777 struct fb_videomode fb_mode;
778 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
780 ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
781 unsigned long di_clk_rate = 65000000;
784 debug("LCD disabled\n");
788 if (tstc() || (wrsr & WRSR_TOUT)) {
789 debug("Disabling LCD\n");
796 vm = getenv("video_mode");
798 debug("Disabling LCD\n");
802 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
804 debug("Using video mode from FDT\n");
806 if (fb_mode.xres < panel_info.vl_col)
807 panel_info.vl_col = fb_mode.xres;
808 if (fb_mode.yres < panel_info.vl_row)
809 panel_info.vl_row = fb_mode.yres;
812 debug("Trying compiled-in video modes\n");
813 while (p->name != NULL) {
814 if (strcmp(p->name, vm) == 0) {
815 debug("Using video mode: '%s'\n", p->name);
822 debug("Trying to decode video_mode: '%s'\n", vm);
823 while (*vm != '\0') {
824 if (*vm >= '0' && *vm <= '9') {
827 val = simple_strtoul(vm, &end, 0);
830 if (val > panel_info.vl_col)
831 val = panel_info.vl_col;
833 panel_info.vl_col = val;
835 } else if (!yres_set) {
836 if (val > panel_info.vl_row)
837 val = panel_info.vl_row;
839 panel_info.vl_row = val;
841 } else if (!bpp_set) {
850 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
851 end - vm, vm, color_depth);
854 } else if (!refresh_set) {
880 pix_fmt = IPU_PIX_FMT_RGB24;
881 tmp = strchr(vm, ':');
889 if (p->xres == 0 || p->yres == 0) {
890 printf("Invalid video mode: %s\n", getenv("video_mode"));
892 printf("Supported video modes are:");
893 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
894 printf(" %s", p->name);
900 p->pixclock = KHZ2PICOS(refresh *
901 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
902 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
904 debug("Pixel clock set to %lu.%03lu MHz\n",
905 PICOS2KHZ(p->pixclock) / 1000,
906 PICOS2KHZ(p->pixclock) % 1000);
908 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
909 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
910 ARRAY_SIZE(stk5_lcd_pads));
912 debug("Initializing FB driver\n");
914 pix_fmt = IPU_PIX_FMT_RGB24;
916 if (karo_load_splashimage(0) == 0) {
917 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
918 u32 ccgr4 = readl(&ccm_regs->CCGR4);
920 /* MIPI HSC clock is required for initialization */
921 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
923 debug("Initializing LCD controller\n");
924 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
926 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
928 debug("Skipping initialization of LCD controller\n");
932 #define lcd_enabled 0
933 #endif /* CONFIG_LCD */
935 static void stk5_board_init(void)
937 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
938 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
941 static void stk5v3_board_init(void)
946 static void tx51_set_cpu_clock(void)
948 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
951 if (tstc() || (wrsr & WRSR_TOUT))
954 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
957 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
959 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
962 printf("CPU clock set to %u.%03u MHz\n",
963 mxc_get_clock(MXC_ARM_CLK) / 1000000,
964 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
967 int board_late_init(void)
970 const char *baseboard;
972 tx51_set_cpu_clock();
975 baseboard = getenv("baseboard");
979 if (strncmp(baseboard, "stk5", 4) == 0) {
980 printf("Baseboard: %s\n", baseboard);
981 if ((strlen(baseboard) == 4) ||
982 strcmp(baseboard, "stk5-v3") == 0) {
984 } else if (strcmp(baseboard, "stk5-v5") == 0) {
985 printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
989 printf("WARNING: Unsupported STK5 board rev.: %s\n",
993 printf("WARNING: Unsupported baseboard: '%s'\n",
999 gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1003 int checkboard(void)
1005 tx51_print_cpuinfo();
1007 printf("Board: Ka-Ro TX51-%sxx%s\n",
1008 TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
1013 #if defined(CONFIG_OF_BOARD_SETUP)
1014 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1015 #include <jffs2/jffs2.h>
1016 #include <mtd_node.h>
1017 struct node_info nodes[] = {
1018 { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1022 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1025 void ft_board_setup(void *blob, bd_t *bd)
1027 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1028 fdt_fixup_ethernet(blob);
1030 karo_fdt_fixup_touchpanel(blob);
1031 karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");