2 #include <configs/tx53.h>
3 #include <asm/arch/imx-regs.h>
5 #define DEBUG_LED_BIT 20
6 #define LED_GPIO_BASE GPIO2_BASE_ADDR
7 #define LED_MUX_OFFSET 0x174
8 #define LED_MUX_MODE 0x11
10 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
12 #ifdef PHYS_SDRAM_2_SIZE
13 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
15 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
19 #define REG_CCGR0 0x68
20 #define REG_CCGR1 0x6c
21 #define REG_CCGR2 0x70
22 #define REG_CCGR3 0x74
23 #define REG_CCGR4 0x78
24 #define REG_CCGR5 0x7c
25 #define REG_CCGR6 0x80
26 #define REG_CCGR7 0x84
27 #define REG_CMEOR 0x88
29 #define CPU_2_BE_32(l) \
30 ((((l) << 24) & 0xFF000000) | \
31 (((l) << 8) & 0x00FF0000) | \
32 (((l) >> 8) & 0x0000FF00) | \
33 (((l) >> 24) & 0x000000FF))
36 CCM register set 0x53FD4000 0x53FD7FFF
37 EIM register set 0x63FDA000 0x63FDAFFF
38 NANDFC register set 0xF7FF0000 0xF7FFFFFF
39 IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF
40 DPLLC1 register 0x63F80000 0x63F83FFF
41 DPLLC2 register 0x63F84000 0x63F87FFF
42 DPLLC3 register 0x63F88000 0x63F8BFFF
43 DPLLC4 register 0x63F8C000 0x63F8FFFF
44 ESD RAM controller register 0x63FD9000 0x63FD9FFF
45 M4IF register 0x63FD8000 0x63FD8FFF
46 DDR 0x70000000 0xEFFFFFFF
47 EIM 0xF0000000 0xF7FEFFFF
48 NANDFC Buffers 0xF7FF0000 0xF7FFFFFF
49 IRAM Free Space 0xF8006000 0xF8017FF0
50 GPU Memory 0xF8020000 0xF805FFFF
52 #define CHECK_DCD_ADDR(a) ( \
53 ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ || \
54 ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ || \
55 ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ || \
56 ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ || \
57 ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \
58 ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ || \
59 ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \
60 ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \
61 ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */)
63 .macro mxc_dcd_item addr, val
64 .ifne CHECK_DCD_ADDR(\addr)
65 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
67 .error "Address \addr not accessible from DCD"
71 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
73 #define MXC_DCD_CMD_SZ_BYTE 1
74 #define MXC_DCD_CMD_SZ_SHORT 2
75 #define MXC_DCD_CMD_SZ_WORD 4
76 #define MXC_DCD_CMD_FLAG_WRITE 0x0
77 #define MXC_DCD_CMD_FLAG_CLR 0x1
78 #define MXC_DCD_CMD_FLAG_SET 0x3
79 #define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
80 #define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
81 #define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
83 #define MXC_DCD_CMD_WRT(type, flags, next) \
84 .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
86 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
87 .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
88 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
90 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
91 .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
92 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
94 #define MXC_DCD_CMD_NOP() \
95 .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
97 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
98 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
99 #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
101 .macro CK_VAL, name, clks, offs, max
105 .ifle \clks - \offs - \max
106 .set \name, \clks - \offs
108 .error "Value \clks out of range for parameter \name"
113 .macro NS_VAL, name, ns, offs, max
117 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
121 .macro CK_MAX, name, ck1, ck2, offs, max
123 CK_VAL \name, \ck1, \offs, \max
125 CK_VAL \name, \ck2, \offs, \max
129 #define ESDMISC_DDR_TYPE_DDR3 0
130 #define ESDMISC_DDR_TYPE_LPDDR2 1
131 #define ESDMISC_DDR_TYPE_DDR2 2
133 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
135 #define CKIL_FREQ_Hz 32768
136 #define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
139 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
140 #define BANK_ADDR_BITS 2
142 #define BANK_ADDR_BITS 1
144 #define SDRAM_BURST_LENGTH 8
148 #define ADDR_MIRROR 0
149 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
151 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
152 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
155 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
156 #define CL_VAL 9 // or 10
158 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
159 #define CL_VAL 7 // or 8
161 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
164 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
168 #error SDRAM clock out of range: 303 .. 800
172 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
173 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
174 CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
175 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
176 NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */
177 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
180 CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
181 CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
182 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
183 CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */
184 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
185 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
186 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
187 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
190 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
191 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
192 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
193 CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */
196 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
197 #define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
198 /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
199 * erroneous Erratum Engcm12377
201 #define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
205 CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
206 CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
207 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
208 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
209 CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
210 CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
213 CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
214 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
215 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
222 #define ESDPDC_VAL_0 ( \
227 (BOTH_CS_PD << 6) | \
232 #define ESDPDC_VAL_1 (ESDPDC_VAL_0 | \
237 #define ROW_ADDR_BITS 14
238 #define COL_ADDR_BITS 10
240 #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
241 #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
242 #define DLL_DISABLE 0
245 .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
246 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
247 ((tWR + 1 - 4) << 9) | \
248 ((((tCL + 3) - 4) & 0x7) << 4) | \
249 ((((tCL + 3) - 4) & 0x8) >> 1))
251 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
252 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
253 (((tWR + 1) / 2) << 9) | \
254 ((((tCL + 3) - 4) & 0x7) << 4) | \
255 ((((tCL + 3) - 4) & 0x8) >> 1))
259 ((Rtt_Nom & 1) << 2) | \
260 (((Rtt_Nom >> 1) & 1) << 6) | \
261 (((Rtt_Nom >> 2) & 1) << 9) | \
262 (DLL_DISABLE << 0) | \
265 (Rtt_WR << 9) /* dynamic ODT */ | \
266 (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
267 (1 << 6) | /* ASR: Automatic Self Refresh */ \
268 (((tCWL + 2) - 5) << 3) | \
272 #define ESDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
273 (1 << 15) /* CON_REQ */ | \
275 (3 << 4) /* MRS command */ | \
280 #define ESDCFG0_VAL ( \
288 #define ESDCFG1_VAL ( \
298 #define ESDCFG2_VAL ( \
304 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
306 #define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
307 ((COL_ADDR_BITS - 9) << 20) | \
308 (BURST_LEN << 19) | \
309 (1 << 16) | /* SDRAM bus width */ \
310 ((-1) << (32 - BANK_ADDR_BITS)))
312 #define ESDMISC_VAL ((ADDR_MIRROR << 19) | \
319 #define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
321 #define ESDOTC_VAL ((tAOFPD << 27) | \
330 .word 0x20424346 /* "FCB " marker */
331 .word 0x01 /* FCB version number */
333 .word 0x0 /* primary image starting page number */
334 .word 0x0 /* secondary image starting page number */
337 .word 0x0 /* DBBT start page (0 == NO DBBT) */
338 .word 0 /* Bad block marker offset in main area (unused) */
340 .word 0 /* BI Swap disabled */
341 .word 0 /* Bad Block marker offset in spare area */
346 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
362 .long CONFIG_U_BOOT_IMG_SIZE
366 #define DCD_VERSION 0x40
369 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
371 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
373 MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
375 /* disable all irrelevant clocks */
376 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff)
377 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffc3)
378 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000)
379 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff)
380 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000)
381 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033)
382 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
383 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
384 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000)
386 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */
388 MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
390 MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */
392 MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */
394 MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */
396 MXC_DCD_ITEM(0x53fd401c, 0xa6a2a020) /* CSCMR1 */
397 MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */
398 MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */
400 #define DDR_SEL_VAL 2
404 #define DDR_SEL_SHIFT 25
407 #define DDR_INPUT_SHIFT 9
413 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
414 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
415 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
417 #define DQM_VAL DSE_MASK
418 #define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT))
419 #define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
420 #define SDCLK_VAL DSE_MASK
421 #define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
423 MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */
424 MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */
425 MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */
426 MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */
427 MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */
428 MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */
430 MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */
431 MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */
432 MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */
433 MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */
435 MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */
436 MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */
437 MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */
438 MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */
440 MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */
441 MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */
443 MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */
444 MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */
446 MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */
447 MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */
449 MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */
450 MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */
452 MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */
453 MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */
454 MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */
455 MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */
456 MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */
457 MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */
459 /* calibration defaults */
460 MXC_DCD_ITEM(0x63fd904c, 0x001f001f)
461 MXC_DCD_ITEM(0x63fd9050, 0x001f001f)
462 MXC_DCD_ITEM(0x63fd907c, 0x011e011e)
463 MXC_DCD_ITEM(0x63fd9080, 0x011f0120)
464 MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b)
465 MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f)
467 MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL)
468 MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
469 MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
470 MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
471 MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
473 MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
474 MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
475 MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
476 MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0)
479 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */
480 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */
481 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */
482 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 0, mr0_val)) /* MRS: MR0 */
483 #if BANK_ADDR_BITS > 1
485 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 2, 0x0000)) /* MRS: MR2 */
486 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 3, 0x0000)) /* MRS: MR3 */
487 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 1, 0x0040)) /* MRS: MR1 */
488 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 0, mr0_val)) /* MRS: MR0 */
490 MXC_DCD_ITEM(0x63fd9020, 3 << 14) /* disable refresh during calibration */
491 MXC_DCD_ITEM(0x63fd9058, 0x00022222)
493 MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
496 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
497 MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
498 MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
500 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
501 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
504 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
505 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val | (1 << 7)) | (1 << 9)) /* MRS: start write leveling */
506 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
507 MXC_DCD_ITEM(0x63fd9048, 0x00000001)
509 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
510 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
511 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
512 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
514 /* DQS calibration */
515 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
516 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
517 MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
519 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
520 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
521 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
523 /* WR DL calibration */
524 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
525 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
526 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
527 MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
528 wr_dl_calib: /* 6c4 */
529 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
530 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
531 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
533 /* RD DL calibration */
534 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
535 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
536 MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
537 rd_dl_calib: /* 70c */
538 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
539 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
540 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
541 MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */
542 MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1)
544 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
548 MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0
549 MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1
550 MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2
551 MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3
552 MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4
553 MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5
554 MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6
555 MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7
556 MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B
557 MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B
558 MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE
559 MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE
560 MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B
561 MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0
562 MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0
564 MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0
565 MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1
566 MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2
567 MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3
568 MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4
569 MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5
570 MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6
571 MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7
572 MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B
573 MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B
574 MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B
575 MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B
576 MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
577 MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
578 MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
580 .ifgt dcd_end - dcd_start - 1768
581 .error "DCD too large!"