2 #include <configs/tx53.h>
3 #include <asm/arch/imx-regs.h>
5 #define DEBUG_LED_BIT 20
6 #define LED_GPIO_BASE GPIO2_BASE_ADDR
7 #define LED_MUX_OFFSET 0x174
8 #define LED_MUX_MODE 0x11
10 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
12 #ifdef PHYS_SDRAM_2_SIZE
13 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
15 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
19 #define REG_CCGR0 0x68
20 #define REG_CCGR1 0x6c
21 #define REG_CCGR2 0x70
22 #define REG_CCGR3 0x74
23 #define REG_CCGR4 0x78
24 #define REG_CCGR5 0x7c
25 #define REG_CCGR6 0x80
26 #define REG_CCGR7 0x84
27 #define REG_CMEOR 0x88
29 #define CPU_2_BE_32(l) \
30 ((((l) << 24) & 0xFF000000) | \
31 (((l) << 8) & 0x00FF0000) | \
32 (((l) >> 8) & 0x0000FF00) | \
33 (((l) >> 24) & 0x000000FF))
35 #define MXC_DCD_ITEM(addr, val) \
36 .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
38 #define MXC_DCD_CMD_SZ_BYTE 1
39 #define MXC_DCD_CMD_SZ_SHORT 2
40 #define MXC_DCD_CMD_SZ_WORD 4
41 #define MXC_DCD_CMD_FLAG_WRITE 0x0
42 #define MXC_DCD_CMD_FLAG_CLR 0x1
43 #define MXC_DCD_CMD_FLAG_SET 0x3
44 #define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
45 #define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
46 #define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
48 #define MXC_DCD_CMD_WRT(type, flags, next) \
49 .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
51 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
52 .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
53 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
55 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
56 .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
57 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
59 #define MXC_DCD_CMD_NOP() \
60 .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
62 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
63 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
65 .macro CK_VAL, name, clks, offs, max
69 .ifle \clks - \offs - \max
70 .set \name, \clks - \offs
72 .error "Value \clks out of range for parameter \name"
77 .macro NS_VAL, name, ns, offs, max
81 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
85 .macro CK_MAX, name, ck1, ck2, offs, max
87 CK_VAL \name, \ck1, \offs, \max
89 CK_VAL \name, \ck2, \offs, \max
93 #define ESDMISC_DDR_TYPE_DDR3 0
94 #define ESDMISC_DDR_TYPE_LPDDR2 1
95 #define ESDMISC_DDR_TYPE_DDR2 2
97 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
99 #define CKIL_FREQ_Hz 32768
100 #define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
103 #if SDRAM_SIZE > RAM_BANK0_SIZE
104 #define BANK_ADDR_BITS 2
106 #define BANK_ADDR_BITS 1
108 #define SDRAM_BURST_LENGTH 8
111 #define ADDR_MIRROR 0
112 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
114 /* 512/1024MiB SDRAM: NT5CB128M16P-CG */
116 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
117 CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
118 CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
119 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
120 NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
121 CK_VAL tCL, 9, 3, 8 /* clks - 3 (0..8) CAS Latency */
124 NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
125 NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
126 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
127 NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
128 CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
129 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
130 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
131 CK_VAL tCWL, 5, 2, 6 /* clks - 2 (0..6) */
134 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
135 CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
136 CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
137 CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
140 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
143 NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
144 NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
145 CK_VAL tANPD, tCWL, 1, 15 /* clks - 1 (0..15) */
146 CK_VAL tAXPD, tCWL, 1, 15 /* clks - 1 (0..15) */
147 CK_VAL tODTLon tCWL - 1, 1, 7 /* clks - 1 (0..7) */
148 CK_VAL tODTLoff tCWL - 1, 1, 31 /* clks - 1 (0..31) */
150 #define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
152 /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
153 * erroneous Erratum Engcm12377
155 #define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
157 #define ROW_ADDR_BITS 14
158 #define COL_ADDR_BITS 10
161 .set mrs_val, (0x8080 | \
162 (3 << 4) /* MRS command */ | \
163 ((1 << 8) /* DLL Reset */ | \
164 ((tWR + 1 - 4) << 9) | \
165 (((tCL + 3) - 4) << 4)) << 16)
167 .set mrs_val, (0x8080 | \
168 (3 << 4) /* MRS command */ | \
169 ((1 << 8) /* DLL Reset */ | \
170 (((tWR + 1) / 2) << 9) | \
171 (((tCL + 3) - 4) << 4)) << 16)
173 #define ESDSCR_MRS_VAL(cs) (mrs_val | ((cs) << 3))
175 #define ESDCFG0_VAL ( \
183 #define ESDCFG1_VAL ( \
193 #define ESDCFG2_VAL ( \
199 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
200 #define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
201 ((COL_ADDR_BITS - 9) << 20) | \
202 (BURST_LEN << 19) | \
203 (1 << 16) | /* SDRAM bus width */ \
204 ((-1) << (32 - BANK_ADDR_BITS)))
206 #define ESDMISC_VAL ((1 << 12) | \
210 (ADDR_MIRROR << 19) | \
213 #define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
215 #define ESDOTC_VAL ((tAOFPD << 27) | \
224 .word 0x20424346 /* "FCB " marker */
225 .word 0x01 /* FCB version number */
227 .word 0x0 /* primary image starting page number */
228 .word 0x0 /* secondary image starting page number */
231 .word 0x0 /* DBBT start page (0 == NO DBBT) */
232 .word 0 /* Bad block marker offset in main area (unused) */
234 .word 0 /* BI Swap disabled */
235 .word 0 /* Bad Block marker offset in spare area */
240 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
256 .long CONFIG_U_BOOT_IMG_SIZE
260 #define DCD_VERSION 0x40
263 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
265 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
266 /* disable all irrelevant clocks */
267 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff)
268 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffc3)
269 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000)
270 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff)
271 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000)
272 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033)
273 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
274 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
275 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000)
277 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */
279 MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
281 MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */
283 MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */
285 MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */
287 MXC_DCD_ITEM(0x53fd401c, 0xa6a2a020) /* CSCMR1 */
288 MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */
289 MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */
291 #define DDR_SEL_VAL 2
295 #define DDR_SEL_SHIFT 25
298 #define DDR_INPUT_SHIFT 9
304 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
305 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
306 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
308 #define DQM_VAL DSE_MASK
309 #define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT))
310 #define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
311 #define SDCLK_VAL DSE_MASK
312 #define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
314 MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */
315 MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */
316 MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */
317 MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */
318 MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */
319 MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */
321 MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */
322 MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */
323 MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */
324 MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */
326 MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */
327 MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */
328 MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */
329 MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */
331 MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */
332 MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */
334 MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */
335 MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */
337 MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */
338 MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */
340 MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */
341 MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */
343 MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */
344 MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */
345 MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */
346 MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */
347 MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */
348 MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */
350 /* calibration defaults */
351 MXC_DCD_ITEM(0x63fd904c, 0x001f001f)
352 MXC_DCD_ITEM(0x63fd9050, 0x001f001f)
353 MXC_DCD_ITEM(0x63fd907c, 0x011e011e)
354 MXC_DCD_ITEM(0x63fd9080, 0x011f0120)
355 MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b)
356 MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f)
358 MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL)
359 MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
360 MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
361 MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
362 MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
364 MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
365 MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
366 MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
367 MXC_DCD_ITEM(0x63fd9004, 0x00030012)
370 MXC_DCD_ITEM(0x63fd901c, 0x00008032) /* MRS: MR2 */
371 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: MR3 */
372 MXC_DCD_ITEM(0x63fd901c, 0x00408031) /* MRS: MR1 */
373 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0)) /* MRS: MR0 */
375 #if BANK_ADDR_BITS > 1
376 MXC_DCD_ITEM(0x63fd901c, 0x0000803a) /* MRS: MR2 */
377 MXC_DCD_ITEM(0x63fd901c, 0x0000803b) /* MRS: MR3 */
378 MXC_DCD_ITEM(0x63fd901c, 0x00408039) /* MRS: MR1 */
379 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1)) /* MRS: MR0 */
381 MXC_DCD_ITEM(0x63fd9020, 0x00005800) /* refresh interval */
382 MXC_DCD_ITEM(0x63fd9058, 0x00011112)
384 MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
387 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
388 MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
389 MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
391 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
392 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
395 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
396 MXC_DCD_ITEM(0x63fd901c, 0x00848231) /* MRS: start write leveling */
397 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
398 MXC_DCD_ITEM(0x63fd9048, 0x00000001)
400 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
401 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
402 MXC_DCD_ITEM(0x63fd901c, 0x00048031) /* MRS: end write leveling */
403 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
405 /* DQS calibration */
406 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
407 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
408 MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
410 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
411 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
412 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
414 /* WR DL calibration */
415 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
416 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
417 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
418 MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
419 wr_dl_calib: /* 6c4 */
420 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
421 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
422 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
424 /* RD DL calibration */
425 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
426 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
427 MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
428 rd_dl_calib: /* 70c */
429 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
430 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
431 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
433 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
435 MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
439 MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0
440 MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1
441 MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2
442 MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3
443 MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4
444 MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5
445 MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6
446 MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7
447 MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B
448 MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B
449 MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE
450 MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE
451 MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B
452 MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0
453 MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0
455 MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0
456 MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1
457 MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2
458 MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3
459 MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4
460 MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5
461 MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6
462 MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7
463 MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B
464 MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B
465 MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B
466 MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B
467 MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
468 MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
469 MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
471 .ifgt dcd_end - dcd_start - 1768
472 .error "DCD too large!"