2 * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
22 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
34 #include <asm/arch/iomux-mx53.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
38 #include <asm/arch/sys_proto.h>
40 #include "../common/karo.h"
42 #define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
43 #define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
44 #define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
45 #define TX53_LED_GPIO IMX_GPIO_NR(2, 20)
47 #define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
48 #define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
51 #define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
53 DECLARE_GLOBAL_DATA_PTR;
55 #define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
58 #define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
59 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
61 static iomux_v3_cfg_t tx53_pads[] = {
62 /* NAND flash pads are set up in lowlevel_init.S */
65 #if CONFIG_MXC_UART_BASE == UART1_BASE
66 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
67 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
68 MX53_PAD_PATA_IORDY__UART1_RTS,
69 MX53_PAD_PATA_RESET_B__UART1_CTS,
71 #if CONFIG_MXC_UART_BASE == UART2_BASE
72 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
73 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
74 MX53_PAD_PATA_DIOR__UART2_RTS,
75 MX53_PAD_PATA_INTRQ__UART2_CTS,
77 #if CONFIG_MXC_UART_BASE == UART3_BASE
78 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
79 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
80 MX53_PAD_PATA_DA_2__UART3_RTS,
81 MX53_PAD_PATA_DA_1__UART3_CTS,
84 MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
85 MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
87 /* FEC PHY GPIO functions */
88 MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
89 MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
90 MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
93 MX53_PAD_FEC_MDC__FEC_MDC,
94 MX53_PAD_FEC_MDIO__FEC_MDIO,
95 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
96 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
97 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
98 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
99 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
100 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
101 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
102 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
105 static const struct gpio tx53_gpios[] = {
106 { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
107 { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
108 { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
109 { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
115 /* placed in section '.data' to prevent overwriting relocation info
118 static u32 wrsr __attribute__((section(".data")));
120 #define WRSR_POR (1 << 4)
121 #define WRSR_TOUT (1 << 1)
122 #define WRSR_SFTW (1 << 0)
124 static void print_reset_cause(void)
126 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
127 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
131 printf("Reset cause: ");
133 srsr = readl(&src_regs->srsr);
134 wrsr = readw(wdt_base + 4);
136 if (wrsr & WRSR_POR) {
137 printf("%sPOR", dlm);
140 if (srsr & 0x00004) {
141 printf("%sCSU", dlm);
144 if (srsr & 0x00008) {
145 printf("%sIPP USER", dlm);
148 if (srsr & 0x00010) {
149 if (wrsr & WRSR_SFTW) {
150 printf("%sSOFT", dlm);
153 if (wrsr & WRSR_TOUT) {
154 printf("%sWDOG", dlm);
158 if (srsr & 0x00020) {
159 printf("%sJTAG HIGH-Z", dlm);
162 if (srsr & 0x00040) {
163 printf("%sJTAG SW", dlm);
166 if (srsr & 0x10000) {
167 printf("%sWARM BOOT", dlm);
176 static void tx53_print_cpuinfo(void)
180 cpurev = get_cpu_rev();
182 printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n",
183 (cpurev & 0x000F0) >> 4,
184 (cpurev & 0x0000F) >> 0,
185 mxc_get_clock(MXC_ARM_CLK) / 1000000);
192 LTC3589_CLIRQ = 0x21,
193 LTC3589_B1DTV1 = 0x23,
194 LTC3589_B1DTV2 = 0x24,
195 LTC3589_VRRCR = 0x25,
196 LTC3589_B2DTV1 = 0x26,
197 LTC3589_B2DTV2 = 0x27,
198 LTC3589_B3DTV1 = 0x29,
199 LTC3589_B3DTV2 = 0x2a,
200 LTC3589_L2DTV1 = 0x32,
201 LTC3589_L2DTV2 = 0x33,
204 #define LTC3589_PGOOD_MASK (1 << 5)
206 #define LTC3589_CLK_RATE_LOW (1 << 5)
208 #define VDD_LDO2_VAL mV_to_regval(vout_to_vref(1325 * 10, 2))
209 #define VDD_CORE_VAL mV_to_regval(vout_to_vref(1240 * 10, 3))
210 #define VDD_SOC_VAL mV_to_regval(vout_to_vref(1325 * 10, 4))
211 #define VDD_BUCK3_VAL mV_to_regval(vout_to_vref(2500 * 10, 5))
213 #ifndef CONFIG_SYS_TX53_HWREV_2
214 /* LDO2 vref divider */
217 /* BUCK1 vref divider */
220 /* BUCK2 vref divider */
223 /* BUCK3 vref divider */
227 /* no dividers on vref */
238 /* calculate voltages in 10mV */
239 #define R1(idx) R1_##idx
240 #define R2(idx) R2_##idx
242 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
243 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
245 #define mV_to_regval(mV) DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
246 #define regval_to_mV(v) (((v) * 125 + 3625))
248 static struct pmic_regs {
249 enum LTC3589_REGS addr;
252 { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
254 { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_PGOOD_MASK, },
255 { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
257 { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_PGOOD_MASK, },
258 { LTC3589_B1DTV2, VDD_CORE_VAL, },
260 { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_PGOOD_MASK, },
261 { LTC3589_B2DTV2, VDD_SOC_VAL, },
263 { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_PGOOD_MASK, },
264 { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
266 { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
269 static int setup_pmic_voltages(void)
275 ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
277 printf("Failed to initialize I2C\n");
281 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
283 printf("%s: i2c_read error: %d\n", __func__, ret);
287 for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
288 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
290 debug("Writing %02x to reg %02x (%02x)\n",
291 ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
292 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
293 <c3589_regs[i].val, 1);
295 printf("%s: failed to write PMIC register %02x: %d\n",
296 __func__, ltc3589_regs[i].addr, ret);
300 printf("VDDCORE set to %umV\n",
301 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
303 printf("VDDSOC set to %umV\n",
304 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
308 int board_early_init_f(void)
310 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
312 gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
313 imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
315 writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
316 writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
318 writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
319 writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
320 writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
321 writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
322 writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
324 writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
325 writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
327 writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
328 writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
329 writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
330 writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
331 writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
333 writel(0xffcf0fff, &ccm_regs->CCGR0);
334 writel(0x000fffc3, &ccm_regs->CCGR1);
335 writel(0x033c0000, &ccm_regs->CCGR2);
336 writel(0x000000ff, &ccm_regs->CCGR3);
337 writel(0x00000000, &ccm_regs->CCGR4);
338 writel(0x00fff033, &ccm_regs->CCGR5);
339 writel(0x0f00030f, &ccm_regs->CCGR6);
340 writel(0xfff00000, &ccm_regs->CCGR7);
341 writel(0x00000000, &ccm_regs->cmeor);
350 /* Address of boot parameters */
351 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
353 if (ctrlc() || (wrsr & WRSR_TOUT)) {
354 printf("CTRL-C detected; Skipping PMIC setup\n");
358 ret = setup_pmic_voltages();
360 printf("Failed to setup PMIC voltages\n");
370 /* dram_init must store complete ramsize in gd->ram_size */
371 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
374 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
375 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
377 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
378 CONFIG_SYS_SDRAM_CLK, ret);
380 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
381 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
382 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
383 CONFIG_SYS_SDRAM_CLK);
387 void dram_init_banksize(void)
389 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
390 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
392 #if CONFIG_NR_DRAM_BANKS > 1
393 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
394 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
399 #ifdef CONFIG_CMD_MMC
400 static const iomux_v3_cfg_t mmc0_pads[] = {
401 MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
402 MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
403 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
404 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
405 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
406 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
408 MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
411 static const iomux_v3_cfg_t mmc1_pads[] = {
412 MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
413 MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
414 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
415 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
416 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
417 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
419 MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
422 static struct tx53_esdhc_cfg {
423 const iomux_v3_cfg_t *pads;
425 struct fsl_esdhc_cfg cfg;
427 } tx53_esdhc_cfg[] = {
430 .num_pads = ARRAY_SIZE(mmc0_pads),
432 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
435 .cd_gpio = IMX_GPIO_NR(3, 24),
439 .num_pads = ARRAY_SIZE(mmc1_pads),
441 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
444 .cd_gpio = IMX_GPIO_NR(3, 25),
448 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
450 return container_of(cfg, struct tx53_esdhc_cfg, cfg);
453 int board_mmc_getcd(struct mmc *mmc)
455 struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
457 if (cfg->cd_gpio < 0)
460 debug("SD card %d is %spresent\n",
461 cfg - tx53_esdhc_cfg,
462 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
463 return !gpio_get_value(cfg->cd_gpio);
466 int board_mmc_init(bd_t *bis)
470 for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
472 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
475 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
478 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
479 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
481 ret = gpio_request_one(cfg->cd_gpio,
482 GPIOF_INPUT, "MMC CD");
484 printf("Error %d requesting GPIO%d_%d\n",
485 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
489 debug("%s: Initializing MMC slot %d\n", __func__, i);
490 fsl_esdhc_initialize(bis, &cfg->cfg);
492 mmc = find_mmc_device(i);
495 if (board_mmc_getcd(mmc) > 0)
500 #endif /* CONFIG_CMD_MMC */
502 #ifdef CONFIG_FEC_MXC
508 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
511 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
512 struct fuse_bank *bank = &iim->bank[1];
513 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
518 for (i = 0; i < ETH_ALEN; i++)
519 mac[i] = readl(&fuse->mac_addr[i]);
522 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
524 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
525 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
527 int board_eth_init(bd_t *bis)
531 /* delay at least 21ms for the PHY internal POR signal to deassert */
534 /* Deassert RESET to the external phy */
535 gpio_set_value(TX53_FEC_RST_GPIO, 1);
537 ret = cpu_eth_init(bis);
539 printf("cpu_eth_init() failed: %d\n", ret);
543 #endif /* CONFIG_FEC_MXC */
551 void show_activity(int arg)
553 static int led_state = LED_STATE_INIT;
556 if (led_state == LED_STATE_INIT) {
558 gpio_set_value(TX53_LED_GPIO, 1);
559 led_state = LED_STATE_ON;
561 if (get_timer(last) > CONFIG_SYS_HZ) {
563 if (led_state == LED_STATE_ON) {
564 gpio_set_value(TX53_LED_GPIO, 0);
566 gpio_set_value(TX53_LED_GPIO, 1);
568 led_state = 1 - led_state;
573 static const iomux_v3_cfg_t stk5_pads[] = {
574 /* SW controlled LED on STK5 baseboard */
575 MX53_PAD_EIM_A18__GPIO2_20,
577 /* I2C bus on DIMM pins 40/41 */
578 MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
579 MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
581 /* TSC200x PEN IRQ */
582 MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
584 /* EDT-FT5x06 Polytouch panel */
585 MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
586 MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
587 MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
590 MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
591 MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
593 MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
594 MX53_PAD_GPIO_8__GPIO1_8, /* OC */
596 /* DS1339 Interrupt */
597 MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
600 static const struct gpio stk5_gpios[] = {
601 { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
603 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
604 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
605 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
606 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
610 vidinfo_t panel_info = {
611 /* set to max. size supported by SoC */
615 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
618 static struct fb_videomode tx53_fb_modes[] = {
619 #ifndef CONFIG_SYS_LVDS_IF
621 /* Standard VGA timing */
626 .pixclock = KHZ2PICOS(25175),
633 .sync = FB_SYNC_CLK_LAT_FALL,
636 /* Emerging ETV570 640 x 480 display. Syncs low active,
637 * DE high active, 115.2 mm x 86.4 mm display area
638 * VGA compatible timing
644 .pixclock = KHZ2PICOS(25175),
651 .sync = FB_SYNC_CLK_LAT_FALL,
654 /* Emerging ET0350G0DH6 320 x 240 display.
655 * 70.08 mm x 52.56 mm display area.
661 .pixclock = KHZ2PICOS(6500),
662 .left_margin = 68 - 34,
665 .upper_margin = 18 - 3,
668 .sync = FB_SYNC_CLK_LAT_FALL,
671 /* Emerging ET0430G0DH6 480 x 272 display.
672 * 95.04 mm x 53.856 mm display area.
678 .pixclock = KHZ2PICOS(9000),
685 .sync = FB_SYNC_CLK_LAT_FALL,
688 /* Emerging ET0500G0DH6 800 x 480 display.
689 * 109.6 mm x 66.4 mm display area.
695 .pixclock = KHZ2PICOS(33260),
696 .left_margin = 216 - 128,
698 .right_margin = 1056 - 800 - 216,
699 .upper_margin = 35 - 2,
701 .lower_margin = 525 - 480 - 35,
702 .sync = FB_SYNC_CLK_LAT_FALL,
705 /* Emerging ETQ570G0DH6 320 x 240 display.
706 * 115.2 mm x 86.4 mm display area.
712 .pixclock = KHZ2PICOS(6400),
716 .upper_margin = 16, /* 15 according to datasheet */
717 .vsync_len = 3, /* TVP -> 1>x>5 */
718 .lower_margin = 4, /* 4.5 according to datasheet */
719 .sync = FB_SYNC_CLK_LAT_FALL,
722 /* Emerging ET0700G0DH6 800 x 480 display.
723 * 152.4 mm x 91.44 mm display area.
729 .pixclock = KHZ2PICOS(33260),
730 .left_margin = 216 - 128,
732 .right_margin = 1056 - 800 - 216,
733 .upper_margin = 35 - 2,
735 .lower_margin = 525 - 480 - 35,
736 .sync = FB_SYNC_CLK_LAT_FALL,
740 /* HannStar HSD100PXN1
741 * 202.7m mm x 152.06 mm display area.
743 .name = "HSD100PXN1",
747 .pixclock = KHZ2PICOS(65000),
754 .sync = FB_SYNC_CLK_LAT_FALL,
758 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
766 .sync = FB_SYNC_CLK_LAT_FALL,
770 static int lcd_enabled = 1;
772 void lcd_enable(void)
775 * global variable from common/lcd.c
776 * Set to 0 here to prevent messages from going to LCD
777 * rather than serial console
782 karo_load_splashimage(1);
784 debug("Switching LCD on\n");
785 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
787 gpio_set_value(TX53_LCD_RST_GPIO, 1);
789 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, is_lvds());
793 void lcd_disable(void)
796 printf("Disabling LCD\n");
801 void lcd_panel_disable(void)
804 debug("Switching LCD off\n");
805 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, !is_lvds());
806 gpio_set_value(TX53_LCD_RST_GPIO, 0);
807 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
811 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
813 MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
814 /* LCD POWER_ENABLE */
815 MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
816 /* LCD Backlight (PWM) */
817 MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
820 #ifndef CONFIG_SYS_LVDS_IF
822 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
823 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
824 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
825 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
826 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
827 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
828 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
829 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
830 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
831 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
832 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
833 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
834 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
835 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
836 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
837 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
838 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
839 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
840 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
841 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
842 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
843 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
844 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
845 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
846 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
847 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
848 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
849 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
852 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
853 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
854 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
855 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
856 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
857 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
858 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
859 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
860 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
861 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
865 static const struct gpio stk5_lcd_gpios[] = {
866 { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
867 { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
868 { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
871 void lcd_ctrl_init(void *lcdbase)
873 int color_depth = 24;
874 const char *video_mode = karo_get_vmode(getenv("video_mode"));
878 struct fb_videomode *p = &tx53_fb_modes[0];
879 struct fb_videomode fb_mode;
880 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
883 ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
884 unsigned long di_clk_rate = 65000000;
887 debug("LCD disabled\n");
891 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
892 debug("Disabling LCD\n");
894 setenv("splashimage", NULL);
900 if (video_mode == NULL) {
901 debug("Disabling LCD\n");
906 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
908 debug("Using video mode from FDT\n");
910 if (fb_mode.xres > panel_info.vl_col ||
911 fb_mode.yres > panel_info.vl_row) {
912 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
913 fb_mode.xres, fb_mode.yres,
914 panel_info.vl_col, panel_info.vl_row);
920 debug("Trying compiled-in video modes\n");
921 while (p->name != NULL) {
922 if (strcmp(p->name, vm) == 0) {
923 debug("Using video mode: '%s'\n", p->name);
930 debug("Trying to decode video_mode: '%s'\n", vm);
931 while (*vm != '\0') {
932 if (*vm >= '0' && *vm <= '9') {
935 val = simple_strtoul(vm, &end, 0);
938 if (val > panel_info.vl_col)
939 val = panel_info.vl_col;
941 panel_info.vl_col = val;
943 } else if (!yres_set) {
944 if (val > panel_info.vl_row)
945 val = panel_info.vl_row;
947 panel_info.vl_row = val;
949 } else if (!bpp_set) {
954 pix_fmt = IPU_PIX_FMT_LVDS888;
968 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
969 end - vm, vm, color_depth);
972 } else if (!refresh_set) {
999 if (p->xres == 0 || p->yres == 0) {
1000 printf("Invalid video mode: %s\n", getenv("video_mode"));
1002 printf("Supported video modes are:");
1003 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1004 printf(" %s", p->name);
1009 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1010 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1011 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1015 panel_info.vl_col = p->xres;
1016 panel_info.vl_row = p->yres;
1018 switch (color_depth) {
1020 panel_info.vl_bpix = LCD_COLOR8;
1023 panel_info.vl_bpix = LCD_COLOR16;
1026 panel_info.vl_bpix = LCD_COLOR24;
1029 p->pixclock = KHZ2PICOS(refresh *
1030 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1031 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
1033 debug("Pixel clock set to %lu.%03lu MHz\n",
1034 PICOS2KHZ(p->pixclock) / 1000,
1035 PICOS2KHZ(p->pixclock) % 1000);
1037 if (p != &fb_mode) {
1040 debug("Creating new display-timing node from '%s'\n",
1042 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1044 printf("Failed to create new display-timing node from '%s': %d\n",
1048 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1049 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1050 ARRAY_SIZE(stk5_lcd_pads));
1052 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1053 switch (lcd_bus_width) {
1055 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1059 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1064 pix_fmt = IPU_PIX_FMT_RGB565;
1070 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1075 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1076 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1079 if (lvds_chan_mask == 0) {
1080 printf("No LVDS channel active\n");
1085 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1086 if (lcd_bus_width == 24)
1087 gpr2 |= (1 << 5) | (1 << 7);
1088 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1089 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1090 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1091 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1093 if (karo_load_splashimage(0) == 0) {
1096 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1098 debug("Initializing LCD controller\n");
1099 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1101 printf("Failed to initialize FB driver: %d\n", ret);
1105 debug("Skipping initialization of LCD controller\n");
1109 #define lcd_enabled 0
1110 #endif /* CONFIG_LCD */
1112 static void stk5_board_init(void)
1114 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1115 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1118 static void stk5v3_board_init(void)
1123 static void stk5v5_board_init(void)
1127 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1128 "Flexcan Transceiver");
1129 imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1132 static void tx53_set_cpu_clock(void)
1134 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1137 if (had_ctrlc() || (wrsr & WRSR_TOUT))
1140 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1143 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
1145 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1148 printf("CPU clock set to %u.%03u MHz\n",
1149 mxc_get_clock(MXC_ARM_CLK) / 1000000,
1150 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
1153 static void tx53_init_mac(void)
1157 imx_get_mac_from_fuse(0, mac);
1158 if (!is_valid_ether_addr(mac)) {
1159 printf("No valid MAC address programmed\n");
1163 printf("MAC addr from fuse: %pM\n", mac);
1164 eth_setenv_enetaddr("ethaddr", mac);
1167 int board_late_init(void)
1170 const char *baseboard;
1172 tx53_set_cpu_clock();
1173 karo_fdt_move_fdt();
1175 baseboard = getenv("baseboard");
1179 if (strncmp(baseboard, "stk5", 4) == 0) {
1180 printf("Baseboard: %s\n", baseboard);
1181 if ((strlen(baseboard) == 4) ||
1182 strcmp(baseboard, "stk5-v3") == 0) {
1183 stk5v3_board_init();
1184 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1185 stk5v5_board_init();
1187 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1191 printf("WARNING: Unsupported baseboard: '%s'\n",
1198 gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1203 int checkboard(void)
1205 tx53_print_cpuinfo();
1207 printf("Board: Ka-Ro TX53-x%d3%s\n",
1208 is_lvds(), TX53_MOD_SUFFIX);
1213 #if defined(CONFIG_OF_BOARD_SETUP)
1214 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1215 #include <jffs2/jffs2.h>
1216 #include <mtd_node.h>
1217 static struct node_info nodes[] = {
1218 { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1222 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1225 #ifdef CONFIG_SYS_TX53_HWREV_2
1226 static void tx53_fixup_rtc(void *blob)
1228 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1229 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1232 static inline void tx53_fixup_rtc(void *blob)
1235 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1237 #ifndef CONFIG_SYS_LVDS_IF
1238 static inline void tx53_fdt_fixup_sata(void *blob)
1240 karo_fdt_enable_node(blob, "/soc/sata", 0);
1243 static inline void tx53_fdt_fixup_sata(void *blob)
1248 static const char *tx53_touchpanels[] = {
1253 void ft_board_setup(void *blob, bd_t *bd)
1255 const char *baseboard = getenv("baseboard");
1256 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1257 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1259 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1260 fdt_fixup_ethernet(blob);
1262 karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1263 ARRAY_SIZE(tx53_touchpanels));
1264 karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1265 karo_fdt_fixup_flexcan(blob, stk5_v5);
1266 tx53_fixup_rtc(blob);
1267 karo_fdt_update_fb_mode(blob, video_mode);
1269 #endif /* CONFIG_OF_BOARD_SETUP */