2 * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
21 #include <fdt_support.h>
25 #include <fsl_esdhc.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
39 #include "../common/karo.h"
41 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
42 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
43 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
44 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
46 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
47 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
48 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
50 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
52 #define TEMPERATURE_MIN -40
53 #define TEMPERATURE_HOT 80
54 #define TEMPERATURE_MAX 125
56 DECLARE_GLOBAL_DATA_PTR;
58 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
62 MX6_PAD_GPIO_17__GPIO_7_12,
65 #if CONFIG_MXC_UART_BASE == UART1_BASE
66 MX6_PAD_SD3_DAT7__UART1_TXD,
67 MX6_PAD_SD3_DAT6__UART1_RXD,
68 MX6_PAD_SD3_DAT1__UART1_RTS,
69 MX6_PAD_SD3_DAT0__UART1_CTS,
71 #if CONFIG_MXC_UART_BASE == UART2_BASE
72 MX6_PAD_SD4_DAT4__UART2_RXD,
73 MX6_PAD_SD4_DAT7__UART2_TXD,
74 MX6_PAD_SD4_DAT5__UART2_RTS,
75 MX6_PAD_SD4_DAT6__UART2_CTS,
77 #if CONFIG_MXC_UART_BASE == UART3_BASE
78 MX6_PAD_EIM_D24__UART3_TXD,
79 MX6_PAD_EIM_D25__UART3_RXD,
80 MX6_PAD_SD3_RST__UART3_RTS,
81 MX6_PAD_SD3_DAT3__UART3_CTS,
84 MX6_PAD_EIM_D28__I2C1_SDA,
85 MX6_PAD_EIM_D21__I2C1_SCL,
87 /* FEC PHY GPIO functions */
88 MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
89 MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
90 MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
93 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
95 MX6_PAD_ENET_MDC__ENET_MDC,
96 MX6_PAD_ENET_MDIO__ENET_MDIO,
97 MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
98 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
99 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
100 MX6_PAD_ENET_RXD1__ENET_RDATA_1,
101 MX6_PAD_ENET_RXD0__ENET_RDATA_0,
102 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
103 MX6_PAD_ENET_TXD1__ENET_TDATA_1,
104 MX6_PAD_ENET_TXD0__ENET_TDATA_0,
107 static const struct gpio tx6qdl_gpios[] = {
108 { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
109 { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
110 { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
111 { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
117 /* placed in section '.data' to prevent overwriting relocation info
120 static u32 wrsr __attribute__((section(".data")));
122 #define WRSR_POR (1 << 4)
123 #define WRSR_TOUT (1 << 1)
124 #define WRSR_SFTW (1 << 0)
126 static void print_reset_cause(void)
128 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
129 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
133 printf("Reset cause: ");
135 srsr = readl(&src_regs->srsr);
136 wrsr = readw(wdt_base + 4);
138 if (wrsr & WRSR_POR) {
139 printf("%sPOR", dlm);
142 if (srsr & 0x00004) {
143 printf("%sCSU", dlm);
146 if (srsr & 0x00008) {
147 printf("%sIPP USER", dlm);
150 if (srsr & 0x00010) {
151 if (wrsr & WRSR_SFTW) {
152 printf("%sSOFT", dlm);
155 if (wrsr & WRSR_TOUT) {
156 printf("%sWDOG", dlm);
160 if (srsr & 0x00020) {
161 printf("%sJTAG HIGH-Z", dlm);
164 if (srsr & 0x00040) {
165 printf("%sJTAG SW", dlm);
168 if (srsr & 0x10000) {
169 printf("%sWARM BOOT", dlm);
178 int read_cpu_temperature(void);
179 int check_cpu_temperature(int boot);
181 static void tx6qdl_print_cpuinfo(void)
183 u32 cpurev = get_cpu_rev();
186 switch ((cpurev >> 12) & 0xff) {
193 case MXC_CPU_MX6SOLO:
201 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
203 (cpurev & 0x000F0) >> 4,
204 (cpurev & 0x0000F) >> 0,
205 mxc_get_clock(MXC_ARM_CLK) / 1000000);
208 check_cpu_temperature(1);
211 #define RN5T618_NOETIMSET 0x11
212 #define RN5T618_LDORTC1_SLOT 0x2a
213 #define RN5T618_DC1CTL 0x2c
214 #define RN5T618_DC1CTL2 0x2d
215 #define RN5T618_DC2CTL 0x2e
216 #define RN5T618_DC2CTL2 0x2f
217 #define RN5T618_DC3CTL 0x30
218 #define RN5T618_DC3CTL2 0x31
219 #define RN5T618_DC1DAC 0x36 /* CORE */
220 #define RN5T618_DC2DAC 0x37 /* SOC */
221 #define RN5T618_DC3DAC 0x38 /* DDR */
222 #define RN5T618_DC1DAC_SLP 0x3b
223 #define RN5T618_DC2DAC_SLP 0x3c
224 #define RN5T618_DC3DAC_SLP 0x3d
225 #define RN5T618_LDOEN1 0x44
226 #define RN5T618_LDODIS 0x46
227 #define RN5T618_LDOEN2 0x48
228 #define RN5T618_LDO3DAC 0x4e /* IO */
229 #define RN5T618_LDORTCDAC 0x56 /* VBACKUP */
231 #define VDD_RTC_VAL mV_to_regval_rtc(3000 * 10)
232 #define VDD_HIGH_VAL mV_to_regval3(3000 * 10)
233 #define VDD_HIGH_VAL_LP mV_to_regval3(3000 * 10)
234 #define VDD_CORE_VAL mV_to_regval(1425 * 10)
235 #define VDD_CORE_VAL_LP mV_to_regval(900 * 10)
236 #define VDD_SOC_VAL mV_to_regval(1425 * 10)
237 #define VDD_SOC_VAL_LP mV_to_regval(900 * 10)
238 #define VDD_DDR_VAL mV_to_regval(1500 * 10)
239 #define VDD_DDR_VAL_LP mV_to_regval(1500 * 10)
241 /* calculate voltages in 10mV */
243 #define mV_to_regval(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 125)
244 #define regval_to_mV(v) (((v) * 125 + 6000))
247 #define mV_to_regval2(mV) DIV_ROUND(((((mV) < 9000) ? 9000 : (mV)) - 9000), 250)
248 #define regval2_to_mV(v) (((v) * 250 + 9000))
251 #define mV_to_regval3(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 250)
252 #define regval3_to_mV(v) (((v) * 250 + 6000))
255 #define mV_to_regval_rtc(mV) DIV_ROUND(((((mV) < 17000) ? 17000 : (mV)) - 17000), 250)
256 #define regval_rtc_to_mV(v) (((v) * 250 + 17000))
258 static struct rn5t618_regs {
263 { RN5T618_NOETIMSET, 0, },
264 { RN5T618_DC1DAC, VDD_CORE_VAL, },
265 { RN5T618_DC2DAC, VDD_SOC_VAL, },
266 { RN5T618_DC3DAC, VDD_DDR_VAL, },
267 { RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, },
268 { RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, },
269 { RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, },
270 { RN5T618_LDOEN1, 0x01f, ~0x1f, },
271 { RN5T618_LDOEN2, 0x10, ~0x30, },
272 { RN5T618_LDODIS, 0x00, },
273 { RN5T618_LDO3DAC, VDD_HIGH_VAL, },
274 { RN5T618_LDORTCDAC, VDD_RTC_VAL, },
275 { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, },
278 static int tx6_rn5t618_setup_regs(struct rn5t618_regs *r, size_t count)
283 for (i = 0; i < count; i++, r++) {
287 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
288 if ((value & ~r->mask) != r->val) {
289 printf("Changing PMIC reg %02x from %02x to %02x\n",
290 r->addr, value, r->val);
293 printf("%s: failed to read PMIC register %02x: %d\n",
294 __func__, r->addr, ret);
298 ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
299 r->addr, 1, &r->val, 1);
301 printf("%s: failed to write PMIC register %02x: %d\n",
302 __func__, r->addr, ret);
306 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
307 printf("PMIC reg %02x is %02x\n", r->addr, value);
313 static int setup_pmic_voltages(void)
318 ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
320 printf("Failed to initialize I2C\n");
324 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
326 printf("%s: i2c_read error: %d\n", __func__, ret);
330 ret = tx6_rn5t618_setup_regs(rn5t618_regs, ARRAY_SIZE(rn5t618_regs));
334 printf("VDDCORE set to %umV\n",
335 DIV_ROUND(regval_to_mV(VDD_CORE_VAL), 10));
336 printf("VDDSOC set to %umV\n",
337 DIV_ROUND(regval_to_mV(VDD_SOC_VAL), 10));
342 int board_early_init_f(void)
344 gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
345 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
354 /* Address of boot parameters */
355 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
356 gd->bd->bi_arch_number = -1;
359 printf("CTRL-C detected; Skipping PMIC setup\n");
363 ret = setup_pmic_voltages();
365 printf("Failed to setup PMIC voltages\n");
373 /* dram_init must store complete ramsize in gd->ram_size */
374 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
379 void dram_init_banksize(void)
381 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
382 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
384 #if CONFIG_NR_DRAM_BANKS > 1
385 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
386 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
391 #ifdef CONFIG_CMD_MMC
392 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
393 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
394 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
396 static const iomux_v3_cfg_t mmc0_pads[] = {
397 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
398 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
399 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
400 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
401 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
402 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
404 MX6_PAD_SD3_CMD__GPIO_7_2,
407 static const iomux_v3_cfg_t mmc1_pads[] = {
408 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
409 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
410 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
411 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
412 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
413 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
415 MX6_PAD_SD3_CLK__GPIO_7_3,
418 static const iomux_v3_cfg_t mmc3_pads[] = {
419 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
420 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
421 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
422 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
423 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
424 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
426 MX6_PAD_NANDF_ALE__USDHC4_RST,
429 static struct tx6_esdhc_cfg {
430 const iomux_v3_cfg_t *pads;
432 enum mxc_clock clkid;
433 struct fsl_esdhc_cfg cfg;
435 } tx6qdl_esdhc_cfg[] = {
438 .num_pads = ARRAY_SIZE(mmc3_pads),
439 .clkid = MXC_ESDHC4_CLK,
441 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
448 .num_pads = ARRAY_SIZE(mmc0_pads),
449 .clkid = MXC_ESDHC_CLK,
451 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
454 .cd_gpio = IMX_GPIO_NR(7, 2),
458 .num_pads = ARRAY_SIZE(mmc1_pads),
459 .clkid = MXC_ESDHC2_CLK,
461 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
464 .cd_gpio = IMX_GPIO_NR(7, 3),
468 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
470 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
473 int board_mmc_getcd(struct mmc *mmc)
475 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
477 if (cfg->cd_gpio < 0)
480 debug("SD card %d is %spresent\n",
481 cfg - tx6qdl_esdhc_cfg,
482 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
483 return !gpio_get_value(cfg->cd_gpio);
486 int board_mmc_init(bd_t *bis)
490 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
492 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
495 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
496 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
498 if (cfg->cd_gpio >= 0) {
499 ret = gpio_request_one(cfg->cd_gpio,
500 GPIOF_INPUT, "MMC CD");
502 printf("Error %d requesting GPIO%d_%d\n",
503 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
508 debug("%s: Initializing MMC slot %d\n", __func__, i);
509 fsl_esdhc_initialize(bis, &cfg->cfg);
511 mmc = find_mmc_device(i);
514 if (board_mmc_getcd(mmc))
519 #endif /* CONFIG_CMD_MMC */
521 #ifdef CONFIG_FEC_MXC
523 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
525 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
526 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
532 int board_eth_init(bd_t *bis)
536 /* delay at least 21ms for the PHY internal POR signal to deassert */
539 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
541 /* Deassert RESET to the external phy */
542 gpio_set_value(TX6_FEC_RST_GPIO, 1);
544 ret = cpu_eth_init(bis);
546 printf("cpu_eth_init() failed: %d\n", ret);
550 #endif /* CONFIG_FEC_MXC */
558 static inline int calc_blink_rate(int tmp)
560 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
561 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
562 (TEMPERATURE_HOT - TEMPERATURE_MIN);
565 void show_activity(int arg)
567 static int led_state = LED_STATE_INIT;
568 static int blink_rate;
571 if (led_state == LED_STATE_INIT) {
573 gpio_set_value(TX6_LED_GPIO, 1);
574 led_state = LED_STATE_ON;
575 blink_rate = calc_blink_rate(check_cpu_temperature(0));
577 if (get_timer(last) > blink_rate) {
578 blink_rate = calc_blink_rate(check_cpu_temperature(0));
579 last = get_timer_masked();
580 if (led_state == LED_STATE_ON) {
581 gpio_set_value(TX6_LED_GPIO, 0);
583 gpio_set_value(TX6_LED_GPIO, 1);
585 led_state = 1 - led_state;
590 static const iomux_v3_cfg_t stk5_pads[] = {
591 /* SW controlled LED on STK5 baseboard */
592 MX6_PAD_EIM_A18__GPIO_2_20,
595 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
596 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
597 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
598 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
599 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
600 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
601 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
602 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
603 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
604 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
605 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
606 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
607 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
608 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
609 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
610 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
611 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
612 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
613 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
614 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
615 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
616 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
617 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
618 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
619 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
620 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
621 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
622 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
624 /* I2C bus on DIMM pins 40/41 */
625 MX6_PAD_GPIO_6__I2C3_SDA,
626 MX6_PAD_GPIO_3__I2C3_SCL,
628 /* TSC200x PEN IRQ */
629 MX6_PAD_EIM_D26__GPIO_3_26,
631 /* EDT-FT5x06 Polytouch panel */
632 MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
633 MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
634 MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
637 MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
638 MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
640 MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
641 MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
642 MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
645 static const struct gpio stk5_gpios[] = {
646 { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
648 { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
649 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
650 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
651 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
652 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
656 static u16 tx6_cmap[256];
657 vidinfo_t panel_info = {
658 /* set to max. size supported by SoC */
662 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
666 static struct fb_videomode tx6_fb_modes[] = {
667 #ifndef CONFIG_SYS_LVDS_IF
669 /* Standard VGA timing */
674 .pixclock = KHZ2PICOS(25175),
681 .sync = FB_SYNC_CLK_LAT_FALL,
684 /* Emerging ETV570 640 x 480 display. Syncs low active,
685 * DE high active, 115.2 mm x 86.4 mm display area
686 * VGA compatible timing
692 .pixclock = KHZ2PICOS(25175),
699 .sync = FB_SYNC_CLK_LAT_FALL,
702 /* Emerging ET0350G0DH6 320 x 240 display.
703 * 70.08 mm x 52.56 mm display area.
709 .pixclock = KHZ2PICOS(6500),
710 .left_margin = 68 - 34,
713 .upper_margin = 18 - 3,
716 .sync = FB_SYNC_CLK_LAT_FALL,
719 /* Emerging ET0430G0DH6 480 x 272 display.
720 * 95.04 mm x 53.856 mm display area.
726 .pixclock = KHZ2PICOS(9000),
733 .sync = FB_SYNC_CLK_LAT_FALL,
736 /* Emerging ET0500G0DH6 800 x 480 display.
737 * 109.6 mm x 66.4 mm display area.
743 .pixclock = KHZ2PICOS(33260),
744 .left_margin = 216 - 128,
746 .right_margin = 1056 - 800 - 216,
747 .upper_margin = 35 - 2,
749 .lower_margin = 525 - 480 - 35,
750 .sync = FB_SYNC_CLK_LAT_FALL,
753 /* Emerging ETQ570G0DH6 320 x 240 display.
754 * 115.2 mm x 86.4 mm display area.
760 .pixclock = KHZ2PICOS(6400),
764 .upper_margin = 16, /* 15 according to datasheet */
765 .vsync_len = 3, /* TVP -> 1>x>5 */
766 .lower_margin = 4, /* 4.5 according to datasheet */
767 .sync = FB_SYNC_CLK_LAT_FALL,
770 /* Emerging ET0700G0DH6 800 x 480 display.
771 * 152.4 mm x 91.44 mm display area.
777 .pixclock = KHZ2PICOS(33260),
778 .left_margin = 216 - 128,
780 .right_margin = 1056 - 800 - 216,
781 .upper_margin = 35 - 2,
783 .lower_margin = 525 - 480 - 35,
784 .sync = FB_SYNC_CLK_LAT_FALL,
787 /* Emerging ET070001DM6 800 x 480 display.
788 * 152.4 mm x 91.44 mm display area.
790 .name = "ET070001DM6",
794 .pixclock = KHZ2PICOS(33260),
795 .left_margin = 216 - 128,
797 .right_margin = 1056 - 800 - 216,
798 .upper_margin = 35 - 2,
800 .lower_margin = 525 - 480 - 35,
805 /* HannStar HSD100PXN1
806 * 202.7m mm x 152.06 mm display area.
808 .name = "HSD100PXN1",
812 .pixclock = KHZ2PICOS(65000),
819 .sync = FB_SYNC_CLK_LAT_FALL,
823 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
831 .sync = FB_SYNC_CLK_LAT_FALL,
835 static int lcd_enabled = 1;
836 static int lcd_bl_polarity;
838 static int lcd_backlight_polarity(void)
840 return lcd_bl_polarity;
843 void lcd_enable(void)
846 * global variable from common/lcd.c
847 * Set to 0 here to prevent messages from going to LCD
848 * rather than serial console
853 karo_load_splashimage(1);
855 debug("Switching LCD on\n");
856 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
858 gpio_set_value(TX6_LCD_RST_GPIO, 1);
860 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, lcd_backlight_polarity());
864 void lcd_disable(void)
867 printf("Disabling LCD\n");
872 void lcd_panel_disable(void)
875 debug("Switching LCD off\n");
876 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, !lcd_backlight_polarity());
877 gpio_set_value(TX6_LCD_RST_GPIO, 0);
878 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
882 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
884 MX6_PAD_EIM_D29__GPIO_3_29,
885 /* LCD POWER_ENABLE */
886 MX6_PAD_EIM_EB3__GPIO_2_31,
887 /* LCD Backlight (PWM) */
888 MX6_PAD_GPIO_1__GPIO_1_1,
891 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
892 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
893 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
894 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
895 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
896 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
897 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
898 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
899 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
900 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
901 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
902 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
903 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
904 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
905 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
906 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
907 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
908 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
909 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
910 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
911 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
912 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
913 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
914 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
915 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
916 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
917 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
918 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
921 static const struct gpio stk5_lcd_gpios[] = {
922 { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
923 { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
924 { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
927 void lcd_ctrl_init(void *lcdbase)
929 int color_depth = 24;
930 const char *video_mode = karo_get_vmode(getenv("video_mode"));
934 struct fb_videomode *p = &tx6_fb_modes[0];
935 struct fb_videomode fb_mode;
936 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
939 unsigned long di_clk_rate = 65000000;
942 debug("LCD disabled\n");
946 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
947 debug("Disabling LCD\n");
949 setenv("splashimage", NULL);
954 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
956 if (video_mode == NULL) {
957 debug("Disabling LCD\n");
962 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
964 debug("Using video mode from FDT\n");
966 if (fb_mode.xres > panel_info.vl_col ||
967 fb_mode.yres > panel_info.vl_row) {
968 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
969 fb_mode.xres, fb_mode.yres,
970 panel_info.vl_col, panel_info.vl_row);
976 debug("Trying compiled-in video modes\n");
977 while (p->name != NULL) {
978 if (strcmp(p->name, vm) == 0) {
979 debug("Using video mode: '%s'\n", p->name);
986 debug("Trying to decode video_mode: '%s'\n", vm);
987 while (*vm != '\0') {
988 if (*vm >= '0' && *vm <= '9') {
991 val = simple_strtoul(vm, &end, 0);
994 if (val > panel_info.vl_col)
995 val = panel_info.vl_col;
997 panel_info.vl_col = val;
999 } else if (!yres_set) {
1000 if (val > panel_info.vl_row)
1001 val = panel_info.vl_row;
1003 panel_info.vl_row = val;
1005 } else if (!bpp_set) {
1010 pix_fmt = IPU_PIX_FMT_LVDS888;
1024 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1025 end - vm, vm, color_depth);
1028 } else if (!refresh_set) {
1055 if (p->xres == 0 || p->yres == 0) {
1056 printf("Invalid video mode: %s\n", getenv("video_mode"));
1058 printf("Supported video modes are:");
1059 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1060 printf(" %s", p->name);
1065 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1066 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1067 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1071 panel_info.vl_col = p->xres;
1072 panel_info.vl_row = p->yres;
1074 switch (color_depth) {
1076 panel_info.vl_bpix = LCD_COLOR8;
1079 panel_info.vl_bpix = LCD_COLOR16;
1082 panel_info.vl_bpix = LCD_COLOR24;
1085 p->pixclock = KHZ2PICOS(refresh *
1086 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1087 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1089 debug("Pixel clock set to %lu.%03lu MHz\n",
1090 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1092 if (p != &fb_mode) {
1095 debug("Creating new display-timing node from '%s'\n",
1097 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1099 printf("Failed to create new display-timing node from '%s': %d\n",
1103 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1104 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1105 ARRAY_SIZE(stk5_lcd_pads));
1107 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1108 switch (lcd_bus_width) {
1110 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1114 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1119 pix_fmt = IPU_PIX_FMT_RGB565;
1125 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1130 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1131 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1134 if (lvds_chan_mask == 0) {
1135 printf("No LVDS channel active\n");
1140 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1141 if (lcd_bus_width == 24)
1142 gpr2 |= (1 << 5) | (1 << 7);
1143 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1144 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1145 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1146 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1148 if (karo_load_splashimage(0) == 0) {
1151 debug("Initializing LCD controller\n");
1152 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
1154 printf("Failed to initialize FB driver: %d\n", ret);
1158 debug("Skipping initialization of LCD controller\n");
1162 #define lcd_enabled 0
1163 #endif /* CONFIG_LCD */
1165 static void stk5_board_init(void)
1167 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1168 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1171 static void stk5v3_board_init(void)
1176 static void stk5v5_board_init(void)
1180 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1181 "Flexcan Transceiver");
1182 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1185 static void tx6qdl_set_cpu_clock(void)
1187 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1189 if (had_ctrlc() || (wrsr & WRSR_TOUT))
1192 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1195 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1196 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1197 printf("CPU clock set to %lu.%03lu MHz\n",
1198 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1200 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1204 static void tx6_init_mac(void)
1208 imx_get_mac_from_fuse(-1, mac);
1209 if (!is_valid_ether_addr(mac)) {
1210 printf("No valid MAC address programmed\n");
1214 printf("MAC addr from fuse: %pM\n", mac);
1215 eth_setenv_enetaddr("ethaddr", mac);
1218 int board_late_init(void)
1221 const char *baseboard;
1223 tx6qdl_set_cpu_clock();
1224 karo_fdt_move_fdt();
1226 baseboard = getenv("baseboard");
1230 printf("Baseboard: %s\n", baseboard);
1232 if (strncmp(baseboard, "stk5", 4) == 0) {
1233 if ((strlen(baseboard) == 4) ||
1234 strcmp(baseboard, "stk5-v3") == 0) {
1235 stk5v3_board_init();
1236 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1237 const char *otg_mode = getenv("otg_mode");
1239 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1240 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1241 otg_mode, baseboard);
1242 setenv("otg_mode", "none");
1244 stk5v5_board_init();
1246 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1250 printf("WARNING: Unsupported baseboard: '%s'\n",
1258 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1263 int checkboard(void)
1265 u32 cpurev = get_cpu_rev();
1266 int cpu_variant = (cpurev >> 12) & 0xff;
1268 tx6qdl_print_cpuinfo();
1270 printf("Board: Ka-Ro TX6%c-%d%d2%d\n",
1271 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1272 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1273 is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64);
1278 #ifdef CONFIG_SERIAL_TAG
1279 void get_board_serial(struct tag_serialnr *serialnr)
1281 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1282 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1284 serialnr->low = readl(&fuse->cfg0);
1285 serialnr->high = readl(&fuse->cfg1);
1289 #ifdef CONFIG_OF_BOARD_SETUP
1290 static const char *tx6_touchpanels[] = {
1296 void ft_board_setup(void *blob, bd_t *bd)
1298 const char *baseboard = getenv("baseboard");
1299 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1300 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1303 ret = fdt_increase_size(blob, 4096);
1305 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1308 karo_fdt_enable_node(blob, "stk5led", 0);
1310 fdt_fixup_ethernet(blob);
1312 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1313 ARRAY_SIZE(tx6_touchpanels));
1314 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1315 karo_fdt_fixup_flexcan(blob, stk5_v5);
1317 karo_fdt_update_fb_mode(blob, video_mode);
1319 #endif /* CONFIG_OF_BOARD_SETUP */