2 * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
20 #include <fdt_support.h>
24 #include <fsl_esdhc.h>
32 #include <asm/arch/mx6-pins.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/hab.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
39 #include "../common/karo.h"
42 #define __data __attribute__((section(".data")))
44 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
45 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
46 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
47 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
49 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
50 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
51 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
53 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
54 #define TX6_I2C1_SCL_GPIO IMX_GPIO_NR(3, 21)
55 #define TX6_I2C1_SDA_GPIO IMX_GPIO_NR(3, 28)
57 #ifdef CONFIG_MX6_TEMPERATURE_MIN
58 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
60 #define TEMPERATURE_MIN (-40)
62 #ifdef CONFIG_MX6_TEMPERATURE_HOT
63 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
65 #define TEMPERATURE_HOT 80
68 DECLARE_GLOBAL_DATA_PTR;
70 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
73 MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
76 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
77 #ifdef CONFIG_SECURE_BOOT
78 char __csf_data[0] __attribute__((section(".__csf_data")));
81 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
83 MX6_PAD_GPIO_17__GPIO7_IO12,
86 #if CONFIG_MXC_UART_BASE == UART1_BASE
87 MX6_PAD_SD3_DAT7__UART1_TX_DATA,
88 MX6_PAD_SD3_DAT6__UART1_RX_DATA,
89 MX6_PAD_SD3_DAT1__UART1_RTS_B,
90 MX6_PAD_SD3_DAT0__UART1_CTS_B,
92 #if CONFIG_MXC_UART_BASE == UART2_BASE
93 MX6_PAD_SD4_DAT4__UART2_RX_DATA,
94 MX6_PAD_SD4_DAT7__UART2_TX_DATA,
95 MX6_PAD_SD4_DAT5__UART2_RTS_B,
96 MX6_PAD_SD4_DAT6__UART2_CTS_B,
98 #if CONFIG_MXC_UART_BASE == UART3_BASE
99 MX6_PAD_EIM_D24__UART3_TX_DATA,
100 MX6_PAD_EIM_D25__UART3_RX_DATA,
101 MX6_PAD_SD3_RST__UART3_RTS_B,
102 MX6_PAD_SD3_DAT3__UART3_CTS_B,
105 MX6_PAD_EIM_D28__I2C1_SDA,
106 MX6_PAD_EIM_D21__I2C1_SCL,
108 /* FEC PHY GPIO functions */
109 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
110 MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
111 MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
114 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
116 MX6_PAD_ENET_MDC__ENET_MDC,
117 MX6_PAD_ENET_MDIO__ENET_MDIO,
118 MX6_PAD_GPIO_16__ENET_REF_CLK,
119 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
120 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
121 MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
122 MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
123 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
124 MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
125 MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
128 #define TX6_I2C_GPIO_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
129 PAD_CTL_SPEED_MED | \
130 PAD_CTL_DSE_34ohm | \
133 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
135 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
136 MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
139 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
141 MX6_PAD_EIM_D28__I2C1_SDA,
142 MX6_PAD_EIM_D21__I2C1_SCL,
145 static const struct gpio const tx6qdl_gpios[] = {
146 /* These two entries are used to forcefully reinitialize the I2C bus */
147 { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
148 { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
150 { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
151 { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
152 { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
153 { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
156 static int pmic_addr __data;
158 #if defined(CONFIG_SOC_MX6Q)
159 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4
160 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4
161 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8
162 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8
163 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898
164 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c
165 #define I2C1_SEL_INPUT_VAL 0
167 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
168 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
169 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174
170 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528
171 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544
172 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868
173 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c
174 #define I2C1_SEL_INPUT_VAL 1
181 static void tx6_i2c_recover(void)
185 #define SCL_BIT (1 << (TX6_I2C1_SCL_GPIO % 32))
186 #define SDA_BIT (1 << (TX6_I2C1_SDA_GPIO % 32))
188 if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
189 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
192 debug("Clearing I2C bus\n");
193 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
194 printf("I2C SCL stuck LOW\n");
197 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
198 GPIO3_BASE_ADDR + GPIO_DR);
199 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
200 GPIO3_BASE_ADDR + GPIO_DIR);
202 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
203 printf("I2C SDA stuck LOW\n");
206 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
207 GPIO3_BASE_ADDR + GPIO_DIR);
208 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
209 GPIO3_BASE_ADDR + GPIO_DR);
210 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
211 GPIO3_BASE_ADDR + GPIO_DIR);
213 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
214 ARRAY_SIZE(tx6_i2c_gpio_pads));
217 for (i = 0; i < 18; i++) {
218 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
220 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
221 writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
224 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
229 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
231 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
232 printf("I2C bus recovery succeeded\n");
234 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
238 debug("Setting up I2C Pads\n");
239 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
240 ARRAY_SIZE(tx6_i2c_pads));
243 /* placed in section '.data' to prevent overwriting relocation info
246 static u32 wrsr __attribute__((section(".data")));
248 #define WRSR_POR (1 << 4)
249 #define WRSR_TOUT (1 << 1)
250 #define WRSR_SFTW (1 << 0)
252 static void print_reset_cause(void)
254 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
255 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
259 printf("Reset cause: ");
261 srsr = readl(&src_regs->srsr);
262 wrsr = readw(wdt_base + 4);
264 if (wrsr & WRSR_POR) {
265 printf("%sPOR", dlm);
268 if (srsr & 0x00004) {
269 printf("%sCSU", dlm);
272 if (srsr & 0x00008) {
273 printf("%sIPP USER", dlm);
276 if (srsr & 0x00010) {
277 if (wrsr & WRSR_SFTW) {
278 printf("%sSOFT", dlm);
281 if (wrsr & WRSR_TOUT) {
282 printf("%sWDOG", dlm);
286 if (srsr & 0x00020) {
287 printf("%sJTAG HIGH-Z", dlm);
290 if (srsr & 0x00040) {
291 printf("%sJTAG SW", dlm);
294 if (srsr & 0x10000) {
295 printf("%sWARM BOOT", dlm);
304 static const char __data *tx6_mod_suffix;
308 u32 cpurev = get_cpu_rev();
311 switch ((cpurev >> 12) & 0xff) {
314 tx6_mod_suffix = "?";
318 tx6_mod_suffix = "U";
320 case MXC_CPU_MX6SOLO:
322 tx6_mod_suffix = "S";
326 tx6_mod_suffix = "Q";
330 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
332 (cpurev & 0x000F0) >> 4,
333 (cpurev & 0x0000F) >> 0,
334 mxc_get_clock(MXC_ARM_CLK) / 1000000);
337 #ifdef CONFIG_MX6_TEMPERATURE_HOT
338 check_cpu_temperature(1);
344 int board_early_init_f(void)
346 debug("%s@%d: \n", __func__, __LINE__);
351 #ifndef CONFIG_MX6_TEMPERATURE_HOT
352 static bool tx6_temp_check_enabled = true;
354 #define tx6_temp_check_enabled 0
357 #ifdef CONFIG_TX6_NAND
358 #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
360 #ifdef CONFIG_MMC_BOOT_SIZE
361 #define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
363 #define TX6_FLASH_SZ 2
365 #endif /* CONFIG_TX6_NAND */
367 #define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
369 static char tx6_mem_table[] = {
370 '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
371 '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
372 '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
373 '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
374 '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
375 '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
376 '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
377 '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
378 '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
379 '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
380 '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
381 '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
393 static inline char tx6_mem_suffix(void)
395 size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
397 debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
398 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
400 if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
403 return tx6_mem_table[mem_idx];
406 static int tx6_get_mod_rev(unsigned int pmic_id)
408 if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
409 return tx6_mod_revs[pmic_id].rev;
414 static int tx6_pmic_probe(void)
418 debug("%s@%d: \n", __func__, __LINE__);
422 for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
423 u8 i2c_addr = tx6_mod_revs[i].addr;
424 int ret = i2c_probe(i2c_addr);
427 debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
430 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
435 static inline int __checkboard(void)
437 u32 cpurev = get_cpu_rev();
438 int cpu_variant = (cpurev >> 12) & 0xff;
441 debug("%s@%d: \n", __func__, __LINE__);
443 pmic_id = tx6_pmic_probe();
445 pmic_addr = tx6_mod_revs[pmic_id].addr;
447 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
449 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
450 is_lvds(), tx6_get_mod_rev(pmic_id),
455 debug("%s@%d: done\n", __func__, __LINE__);
462 u32 cpurev = get_cpu_rev();
463 int cpu_variant = (cpurev >> 12) & 0xff;
466 debug("%s@%d: \n", __func__, __LINE__);
468 pmic_id = tx6_pmic_probe();
470 pmic_addr = tx6_mod_revs[pmic_id].addr;
472 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
474 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
475 is_lvds(), tx6_get_mod_rev(pmic_id),
480 ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
482 printf("Failed to request tx6qdl_gpios: %d\n", ret);
484 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
486 /* Address of boot parameters */
487 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
488 gd->bd->bi_arch_number = -1;
490 if (ctrlc() || (wrsr & WRSR_TOUT)) {
491 if (wrsr & WRSR_TOUT)
492 printf("WDOG RESET detected; Skipping PMIC setup\n");
494 printf("<CTRL-C> detected; safeboot enabled\n");
495 #ifndef CONFIG_MX6_TEMPERATURE_HOT
496 tx6_temp_check_enabled = false;
501 ret = tx6_pmic_init(pmic_addr);
503 printf("Failed to setup PMIC voltages: %d\n", ret);
511 debug("%s@%d: \n", __func__, __LINE__);
513 /* dram_init must store complete ramsize in gd->ram_size */
514 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
515 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
519 void dram_init_banksize(void)
521 debug("%s@%d: \n", __func__, __LINE__);
523 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
524 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
526 #if CONFIG_NR_DRAM_BANKS > 1
527 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
528 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
533 #ifdef CONFIG_FSL_ESDHC
534 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
535 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
538 static const iomux_v3_cfg_t mmc0_pads[] = {
539 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
540 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
541 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
542 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
543 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
544 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
546 MX6_PAD_SD3_CMD__GPIO7_IO02,
549 static const iomux_v3_cfg_t mmc1_pads[] = {
550 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
551 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
552 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
553 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
554 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
555 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
557 MX6_PAD_SD3_CLK__GPIO7_IO03,
560 #ifdef CONFIG_TX6_EMMC
561 static const iomux_v3_cfg_t mmc3_pads[] = {
562 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
563 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
564 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
565 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
566 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
567 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
569 MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
574 static struct tx6_esdhc_cfg {
575 const iomux_v3_cfg_t *pads;
577 enum mxc_clock clkid;
578 struct fsl_esdhc_cfg cfg;
580 } tx6qdl_esdhc_cfg[] = {
581 #ifdef CONFIG_TX6_EMMC
584 .num_pads = ARRAY_SIZE(mmc3_pads),
585 .clkid = MXC_ESDHC4_CLK,
587 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
595 .num_pads = ARRAY_SIZE(mmc0_pads),
596 .clkid = MXC_ESDHC_CLK,
598 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
601 .cd_gpio = IMX_GPIO_NR(7, 2),
605 .num_pads = ARRAY_SIZE(mmc1_pads),
606 .clkid = MXC_ESDHC2_CLK,
608 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
611 .cd_gpio = IMX_GPIO_NR(7, 3),
615 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
617 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
620 int board_mmc_getcd(struct mmc *mmc)
622 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
624 if (cfg->cd_gpio < 0)
627 debug("SD card %d is %spresent (GPIO %d)\n",
628 cfg - tx6qdl_esdhc_cfg,
629 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
631 return !gpio_get_value(cfg->cd_gpio);
634 int board_mmc_init(bd_t *bis)
638 debug("%s@%d: \n", __func__, __LINE__);
640 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
642 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
645 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
646 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
648 if (cfg->cd_gpio >= 0) {
649 ret = gpio_request_one(cfg->cd_gpio,
650 GPIOFLAG_INPUT, "MMC CD");
652 printf("Error %d requesting GPIO%d_%d\n",
653 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
658 debug("%s: Initializing MMC slot %d\n", __func__, i);
659 fsl_esdhc_initialize(bis, &cfg->cfg);
661 mmc = find_mmc_device(i);
664 if (board_mmc_getcd(mmc))
669 #endif /* CONFIG_CMD_MMC */
671 #ifdef CONFIG_FEC_MXC
677 int board_eth_init(bd_t *bis)
681 debug("%s@%d: \n", __func__, __LINE__);
683 /* delay at least 21ms for the PHY internal POR signal to deassert */
686 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
687 ARRAY_SIZE(tx6qdl_fec_pads));
689 /* Deassert RESET to the external phy */
690 gpio_set_value(TX6_FEC_RST_GPIO, 1);
692 ret = cpu_eth_init(bis);
694 printf("cpu_eth_init() failed: %d\n", ret);
699 static void tx6_init_mac(void)
703 imx_get_mac_from_fuse(-1, mac);
704 if (!is_valid_ethaddr(mac)) {
705 printf("No valid MAC address programmed\n");
709 printf("MAC addr from fuse: %pM\n", mac);
710 eth_setenv_enetaddr("ethaddr", mac);
713 static inline void tx6_init_mac(void)
716 #endif /* CONFIG_FEC_MXC */
724 static inline int calc_blink_rate(void)
726 if (!tx6_temp_check_enabled)
727 return CONFIG_SYS_HZ;
729 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
730 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
731 (TEMPERATURE_HOT - TEMPERATURE_MIN);
734 void show_activity(int arg)
736 static int led_state = LED_STATE_INIT;
737 static int blink_rate;
740 if (led_state == LED_STATE_INIT) {
742 gpio_set_value(TX6_LED_GPIO, 1);
743 led_state = LED_STATE_ON;
744 blink_rate = calc_blink_rate();
746 if (get_timer(last) > blink_rate) {
747 blink_rate = calc_blink_rate();
748 last = get_timer_masked();
749 if (led_state == LED_STATE_ON) {
750 gpio_set_value(TX6_LED_GPIO, 0);
752 gpio_set_value(TX6_LED_GPIO, 1);
754 led_state = 1 - led_state;
759 static const iomux_v3_cfg_t stk5_pads[] = {
760 /* SW controlled LED on STK5 baseboard */
761 MX6_PAD_EIM_A18__GPIO2_IO20,
763 /* I2C bus on DIMM pins 40/41 */
764 MX6_PAD_GPIO_6__I2C3_SDA,
765 MX6_PAD_GPIO_3__I2C3_SCL,
767 /* TSC200x PEN IRQ */
768 MX6_PAD_EIM_D26__GPIO3_IO26,
770 /* EDT-FT5x06 Polytouch panel */
771 MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
772 MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
773 MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
776 MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
777 MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
779 MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
780 MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
781 MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
784 static const struct gpio stk5_gpios[] = {
785 { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
787 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
788 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
789 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
790 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
791 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
795 static u16 tx6_cmap[256];
796 vidinfo_t panel_info = {
797 /* set to max. size supported by SoC */
801 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
805 static struct fb_videomode tx6_fb_modes[] = {
806 #ifndef CONFIG_SYS_LVDS_IF
808 /* Standard VGA timing */
813 .pixclock = KHZ2PICOS(25175),
820 .sync = FB_SYNC_CLK_LAT_FALL,
823 /* Emerging ETV570 640 x 480 display. Syncs low active,
824 * DE high active, 115.2 mm x 86.4 mm display area
825 * VGA compatible timing
831 .pixclock = KHZ2PICOS(25175),
838 .sync = FB_SYNC_CLK_LAT_FALL,
841 /* Emerging ET0350G0DH6 320 x 240 display.
842 * 70.08 mm x 52.56 mm display area.
848 .pixclock = KHZ2PICOS(6500),
849 .left_margin = 68 - 34,
852 .upper_margin = 18 - 3,
855 .sync = FB_SYNC_CLK_LAT_FALL,
858 /* Emerging ET0430G0DH6 480 x 272 display.
859 * 95.04 mm x 53.856 mm display area.
865 .pixclock = KHZ2PICOS(9000),
874 /* Emerging ET0500G0DH6 800 x 480 display.
875 * 109.6 mm x 66.4 mm display area.
881 .pixclock = KHZ2PICOS(33260),
882 .left_margin = 216 - 128,
884 .right_margin = 1056 - 800 - 216,
885 .upper_margin = 35 - 2,
887 .lower_margin = 525 - 480 - 35,
888 .sync = FB_SYNC_CLK_LAT_FALL,
891 /* Emerging ETQ570G0DH6 320 x 240 display.
892 * 115.2 mm x 86.4 mm display area.
898 .pixclock = KHZ2PICOS(6400),
902 .upper_margin = 16, /* 15 according to datasheet */
903 .vsync_len = 3, /* TVP -> 1>x>5 */
904 .lower_margin = 4, /* 4.5 according to datasheet */
905 .sync = FB_SYNC_CLK_LAT_FALL,
908 /* Emerging ET0700G0DH6 800 x 480 display.
909 * 152.4 mm x 91.44 mm display area.
915 .pixclock = KHZ2PICOS(33260),
916 .left_margin = 216 - 128,
918 .right_margin = 1056 - 800 - 216,
919 .upper_margin = 35 - 2,
921 .lower_margin = 525 - 480 - 35,
922 .sync = FB_SYNC_CLK_LAT_FALL,
925 /* Emerging ET070001DM6 800 x 480 display.
926 * 152.4 mm x 91.44 mm display area.
928 .name = "ET070001DM6",
932 .pixclock = KHZ2PICOS(33260),
933 .left_margin = 216 - 128,
935 .right_margin = 1056 - 800 - 216,
936 .upper_margin = 35 - 2,
938 .lower_margin = 525 - 480 - 35,
943 /* HannStar HSD100PXN1
944 * 202.7m mm x 152.06 mm display area.
946 .name = "HSD100PXN1",
950 .pixclock = KHZ2PICOS(65000),
957 .sync = FB_SYNC_CLK_LAT_FALL,
961 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
969 .sync = FB_SYNC_CLK_LAT_FALL,
973 static int lcd_enabled = 1;
974 static int lcd_bl_polarity;
976 static int lcd_backlight_polarity(void)
978 return lcd_bl_polarity;
981 void lcd_enable(void)
984 * global variable from common/lcd.c
985 * Set to 0 here to prevent messages from going to LCD
986 * rather than serial console
991 karo_load_splashimage(1);
993 debug("Switching LCD on\n");
994 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
996 gpio_set_value(TX6_LCD_RST_GPIO, 1);
998 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
999 lcd_backlight_polarity());
1003 void lcd_disable(void)
1006 printf("Disabling LCD\n");
1007 ipuv3_fb_shutdown();
1011 void lcd_panel_disable(void)
1014 debug("Switching LCD off\n");
1015 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1016 !lcd_backlight_polarity());
1017 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1018 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1022 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1024 MX6_PAD_EIM_D29__GPIO3_IO29,
1025 /* LCD POWER_ENABLE */
1026 MX6_PAD_EIM_EB3__GPIO2_IO31,
1027 /* LCD Backlight (PWM) */
1028 MX6_PAD_GPIO_1__GPIO1_IO01,
1030 #ifndef CONFIG_SYS_LVDS_IF
1032 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1033 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1034 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1035 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1036 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1037 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1038 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1039 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1040 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1041 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1042 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1043 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1044 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1045 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1046 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1047 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1048 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1049 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1050 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1051 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1052 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1053 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1054 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1055 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1056 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1057 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1058 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1059 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1063 static const struct gpio stk5_lcd_gpios[] = {
1064 { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1065 { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1066 { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1069 void lcd_ctrl_init(void *lcdbase)
1071 int color_depth = 24;
1072 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1076 struct fb_videomode *p = &tx6_fb_modes[0];
1077 struct fb_videomode fb_mode;
1078 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1081 unsigned long di_clk_rate = 65000000;
1084 debug("LCD disabled\n");
1088 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1089 debug("Disabling LCD\n");
1091 setenv("splashimage", NULL);
1095 karo_fdt_move_fdt();
1096 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1098 if (video_mode == NULL) {
1099 debug("Disabling LCD\n");
1104 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1106 debug("Using video mode from FDT\n");
1108 if (fb_mode.xres > panel_info.vl_col ||
1109 fb_mode.yres > panel_info.vl_row) {
1110 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1111 fb_mode.xres, fb_mode.yres,
1112 panel_info.vl_col, panel_info.vl_row);
1117 if (p->name != NULL)
1118 debug("Trying compiled-in video modes\n");
1119 while (p->name != NULL) {
1120 if (strcmp(p->name, vm) == 0) {
1121 debug("Using video mode: '%s'\n", p->name);
1128 debug("Trying to decode video_mode: '%s'\n", vm);
1129 while (*vm != '\0') {
1130 if (*vm >= '0' && *vm <= '9') {
1133 val = simple_strtoul(vm, &end, 0);
1136 if (val > panel_info.vl_col)
1137 val = panel_info.vl_col;
1139 panel_info.vl_col = val;
1141 } else if (!yres_set) {
1142 if (val > panel_info.vl_row)
1143 val = panel_info.vl_row;
1145 panel_info.vl_row = val;
1147 } else if (!bpp_set) {
1152 pix_fmt = IPU_PIX_FMT_LVDS888;
1166 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1167 end - vm, vm, color_depth);
1170 } else if (!refresh_set) {
1197 if (p->xres == 0 || p->yres == 0) {
1198 printf("Invalid video mode: %s\n", getenv("video_mode"));
1200 printf("Supported video modes are:");
1201 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1202 printf(" %s", p->name);
1207 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1208 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1209 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1213 panel_info.vl_col = p->xres;
1214 panel_info.vl_row = p->yres;
1216 switch (color_depth) {
1218 panel_info.vl_bpix = LCD_COLOR8;
1221 panel_info.vl_bpix = LCD_COLOR16;
1224 panel_info.vl_bpix = LCD_COLOR32;
1227 p->pixclock = KHZ2PICOS(refresh *
1228 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1229 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1231 debug("Pixel clock set to %lu.%03lu MHz\n",
1232 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1234 if (p != &fb_mode) {
1237 debug("Creating new display-timing node from '%s'\n",
1239 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1241 printf("Failed to create new display-timing node from '%s': %d\n",
1245 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1246 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1247 ARRAY_SIZE(stk5_lcd_pads));
1249 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1250 switch (lcd_bus_width) {
1252 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1256 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1261 pix_fmt = IPU_PIX_FMT_RGB565;
1267 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1272 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1273 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1277 if (lvds_chan_mask == 0) {
1278 printf("No LVDS channel active\n");
1283 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1284 if (lcd_bus_width == 24)
1285 gpr2 |= (1 << 5) | (1 << 7);
1286 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1287 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1288 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1289 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1291 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1292 gpr3 &= ~((3 << 8) | (3 << 6));
1293 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1295 if (karo_load_splashimage(0) == 0) {
1298 debug("Initializing LCD controller\n");
1299 ret = ipuv3_fb_init(p, 0, pix_fmt,
1300 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1303 printf("Failed to initialize FB driver: %d\n", ret);
1307 debug("Skipping initialization of LCD controller\n");
1311 #define lcd_enabled 0
1312 #endif /* CONFIG_LCD */
1314 static void stk5_board_init(void)
1318 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1320 printf("Failed to request stk5_gpios: %d\n", ret);
1323 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1326 static void stk5v3_board_init(void)
1331 static void stk5v5_board_init(void)
1337 ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1338 "Flexcan Transceiver");
1340 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1344 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1347 static void tx6qdl_set_cpu_clock(void)
1349 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1351 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1354 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1355 printf("%s detected; skipping cpu clock change\n",
1356 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1359 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1360 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1361 printf("CPU clock set to %lu.%03lu MHz\n",
1362 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1364 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1368 int board_late_init(void)
1371 const char *baseboard;
1373 /* override secure_boot fuse */
1374 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1375 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1377 writel(0x12, &fuse->cfg5);
1380 debug("%s@%d: \n", __func__, __LINE__);
1384 if (tx6_temp_check_enabled)
1385 check_cpu_temperature(1);
1387 tx6qdl_set_cpu_clock();
1390 setenv_ulong("safeboot", 1);
1391 else if (wrsr & WRSR_TOUT)
1392 setenv_ulong("wdreset", 1);
1394 karo_fdt_move_fdt();
1396 baseboard = getenv("baseboard");
1400 printf("Baseboard: %s\n", baseboard);
1402 if (strncmp(baseboard, "stk5", 4) == 0) {
1403 if ((strlen(baseboard) == 4) ||
1404 strcmp(baseboard, "stk5-v3") == 0) {
1405 stk5v3_board_init();
1406 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1407 const char *otg_mode = getenv("otg_mode");
1409 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1410 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1411 otg_mode, baseboard);
1412 setenv("otg_mode", "none");
1414 stk5v5_board_init();
1416 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1420 printf("WARNING: Unsupported baseboard: '%s'\n",
1428 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1433 #ifdef CONFIG_SERIAL_TAG
1434 void get_board_serial(struct tag_serialnr *serialnr)
1436 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1437 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1439 serialnr->low = readl(&fuse->cfg0);
1440 serialnr->high = readl(&fuse->cfg1);
1444 #if defined(CONFIG_OF_BOARD_SETUP)
1445 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1446 #include <jffs2/jffs2.h>
1447 #include <mtd_node.h>
1448 static struct node_info nodes[] = {
1449 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1452 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1455 static const char *tx6_touchpanels[] = {
1461 int ft_board_setup(void *blob, bd_t *bd)
1463 const char *baseboard = getenv("baseboard");
1464 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1465 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1468 ret = fdt_increase_size(blob, 4096);
1470 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1474 karo_fdt_enable_node(blob, "stk5led", 0);
1476 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1477 fdt_fixup_ethernet(blob);
1479 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1480 ARRAY_SIZE(tx6_touchpanels));
1481 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1482 karo_fdt_fixup_flexcan(blob, stk5_v5);
1484 karo_fdt_update_fb_mode(blob, video_mode);
1488 #endif /* CONFIG_OF_BOARD_SETUP */