2 * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
20 #include <fdt_support.h>
24 #include <fsl_esdhc.h>
32 #include <asm/arch/mx6-pins.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/imx-regs.h>
35 #include <asm/arch/crm_regs.h>
36 #include <asm/arch/sys_proto.h>
38 #include "../common/karo.h"
41 #define __data __attribute__((section(".data")))
43 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
44 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
45 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
46 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
48 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
49 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
50 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
52 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
57 #define TEMPERATURE_MIN (-40)
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
62 #define TEMPERATURE_HOT 80
65 DECLARE_GLOBAL_DATA_PTR;
67 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
70 MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
73 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
75 #ifdef CONFIG_TX6_NAND_
77 MX6_PAD_NANDF_CLE__NAND_CLE,
78 MX6_PAD_NANDF_ALE__NAND_ALE,
79 MX6_PAD_NANDF_WP_B__NAND_RESETN,
80 MX6_PAD_NANDF_RB0__NAND_READY0,
81 MX6_PAD_NANDF_CS0__NAND_CE0N,
82 MX6_PAD_SD4_CMD__NAND_RDN,
83 MX6_PAD_SD4_CLK__NAND_WRN,
84 MX6_PAD_NANDF_D0__NAND_D0,
85 MX6_PAD_NANDF_D1__NAND_D1,
86 MX6_PAD_NANDF_D2__NAND_D2,
87 MX6_PAD_NANDF_D3__NAND_D3,
88 MX6_PAD_NANDF_D4__NAND_D4,
89 MX6_PAD_NANDF_D5__NAND_D5,
90 MX6_PAD_NANDF_D6__NAND_D6,
91 MX6_PAD_NANDF_D7__NAND_D7,
94 MX6_PAD_GPIO_17__GPIO7_IO12,
97 #if CONFIG_MXC_UART_BASE == UART1_BASE
98 MX6_PAD_SD3_DAT7__UART1_TX_DATA,
99 MX6_PAD_SD3_DAT6__UART1_RX_DATA,
100 MX6_PAD_SD3_DAT1__UART1_RTS_B,
101 MX6_PAD_SD3_DAT0__UART1_CTS_B,
103 #if CONFIG_MXC_UART_BASE == UART2_BASE
104 MX6_PAD_SD4_DAT4__UART2_RX_DATA,
105 MX6_PAD_SD4_DAT7__UART2_TX_DATA,
106 MX6_PAD_SD4_DAT5__UART2_RTS_B,
107 MX6_PAD_SD4_DAT6__UART2_CTS_B,
109 #if CONFIG_MXC_UART_BASE == UART3_BASE
110 MX6_PAD_EIM_D24__UART3_TX_DATA,
111 MX6_PAD_EIM_D25__UART3_RX_DATA,
112 MX6_PAD_SD3_RST__UART3_RTS_B,
113 MX6_PAD_SD3_DAT3__UART3_CTS_B,
116 MX6_PAD_EIM_D28__I2C1_SDA,
117 MX6_PAD_EIM_D21__I2C1_SCL,
119 /* FEC PHY GPIO functions */
120 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
121 MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
122 MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
125 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
127 MX6_PAD_ENET_MDC__ENET_MDC,
128 MX6_PAD_ENET_MDIO__ENET_MDIO,
129 MX6_PAD_GPIO_16__ENET_REF_CLK,
130 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
131 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
132 MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
133 MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
134 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
135 MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
136 MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
139 static const struct gpio const tx6qdl_gpios[] = {
140 { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
141 { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
142 { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
143 { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
149 /* placed in section '.data' to prevent overwriting relocation info
152 static u32 wrsr __attribute__((section(".data")));
154 #define WRSR_POR (1 << 4)
155 #define WRSR_TOUT (1 << 1)
156 #define WRSR_SFTW (1 << 0)
158 static void print_reset_cause(void)
160 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
161 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
165 printf("Reset cause: ");
167 srsr = readl(&src_regs->srsr);
168 wrsr = readw(wdt_base + 4);
170 if (wrsr & WRSR_POR) {
171 printf("%sPOR", dlm);
174 if (srsr & 0x00004) {
175 printf("%sCSU", dlm);
178 if (srsr & 0x00008) {
179 printf("%sIPP USER", dlm);
182 if (srsr & 0x00010) {
183 if (wrsr & WRSR_SFTW) {
184 printf("%sSOFT", dlm);
187 if (wrsr & WRSR_TOUT) {
188 printf("%sWDOG", dlm);
192 if (srsr & 0x00020) {
193 printf("%sJTAG HIGH-Z", dlm);
196 if (srsr & 0x00040) {
197 printf("%sJTAG SW", dlm);
200 if (srsr & 0x10000) {
201 printf("%sWARM BOOT", dlm);
210 static const char __data *tx6_mod_suffix;
212 static void tx6qdl_print_cpuinfo(void)
214 u32 cpurev = get_cpu_rev();
217 switch ((cpurev >> 12) & 0xff) {
220 tx6_mod_suffix = "?";
224 tx6_mod_suffix = "U";
226 case MXC_CPU_MX6SOLO:
228 tx6_mod_suffix = "S";
232 tx6_mod_suffix = "Q";
236 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
238 (cpurev & 0x000F0) >> 4,
239 (cpurev & 0x0000F) >> 0,
240 mxc_get_clock(MXC_ARM_CLK) / 1000000);
243 #ifdef CONFIG_MX6_TEMPERATURE_HOT
244 check_cpu_temperature(1);
248 int board_early_init_f(void)
250 gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
251 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
256 #ifndef CONFIG_MX6_TEMPERATURE_HOT
257 static bool tx6_temp_check_enabled = true;
259 #define tx6_temp_check_enabled 0
266 /* Address of boot parameters */
267 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
268 gd->bd->bi_arch_number = -1;
270 if (ctrlc() || (wrsr & WRSR_TOUT)) {
271 if (wrsr & WRSR_TOUT)
272 printf("WDOG RESET detected; Skipping PMIC setup\n");
274 printf("<CTRL-C> detected; safeboot enabled\n");
275 #ifndef CONFIG_MX6_TEMPERATURE_HOT
276 tx6_temp_check_enabled = false;
281 ret = tx6_pmic_init();
283 printf("Failed to setup PMIC voltages\n");
291 /* dram_init must store complete ramsize in gd->ram_size */
292 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
297 void dram_init_banksize(void)
299 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
300 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
302 #if CONFIG_NR_DRAM_BANKS > 1
303 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
304 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
309 #ifdef CONFIG_CMD_MMC
310 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
311 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
314 static const iomux_v3_cfg_t mmc0_pads[] = {
315 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
316 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
317 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
318 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
319 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
320 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
322 MX6_PAD_SD3_CMD__GPIO7_IO02,
325 static const iomux_v3_cfg_t mmc1_pads[] = {
326 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
327 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
328 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
329 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
330 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
331 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
333 MX6_PAD_SD3_CLK__GPIO7_IO03,
336 #ifdef CONFIG_TX6_EMMC
337 static const iomux_v3_cfg_t mmc3_pads[] = {
338 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
339 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
340 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
341 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
342 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
343 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
345 MX6_PAD_NANDF_ALE__SD4_RESET,
349 static struct tx6_esdhc_cfg {
350 const iomux_v3_cfg_t *pads;
352 enum mxc_clock clkid;
353 struct fsl_esdhc_cfg cfg;
355 } tx6qdl_esdhc_cfg[] = {
356 #ifdef CONFIG_TX6_EMMC
359 .num_pads = ARRAY_SIZE(mmc3_pads),
360 .clkid = MXC_ESDHC4_CLK,
362 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
370 .num_pads = ARRAY_SIZE(mmc0_pads),
371 .clkid = MXC_ESDHC_CLK,
373 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
376 .cd_gpio = IMX_GPIO_NR(7, 2),
380 .num_pads = ARRAY_SIZE(mmc1_pads),
381 .clkid = MXC_ESDHC2_CLK,
383 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
386 .cd_gpio = IMX_GPIO_NR(7, 3),
390 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
392 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
395 int board_mmc_getcd(struct mmc *mmc)
397 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
399 if (cfg->cd_gpio < 0)
402 debug("SD card %d is %spresent (GPIO %d)\n",
403 cfg - tx6qdl_esdhc_cfg,
404 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
406 return !gpio_get_value(cfg->cd_gpio);
409 int board_mmc_init(bd_t *bis)
413 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
415 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
418 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
419 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
421 if (cfg->cd_gpio >= 0) {
422 ret = gpio_request_one(cfg->cd_gpio,
423 GPIOFLAG_INPUT, "MMC CD");
425 printf("Error %d requesting GPIO%d_%d\n",
426 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
431 debug("%s: Initializing MMC slot %d\n", __func__, i);
432 fsl_esdhc_initialize(bis, &cfg->cfg);
434 mmc = find_mmc_device(i);
437 if (board_mmc_getcd(mmc))
442 #endif /* CONFIG_CMD_MMC */
444 #ifdef CONFIG_FEC_MXC
446 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
448 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
449 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
455 int board_eth_init(bd_t *bis)
459 /* delay at least 21ms for the PHY internal POR signal to deassert */
462 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
463 ARRAY_SIZE(tx6qdl_fec_pads));
465 /* Deassert RESET to the external phy */
466 gpio_set_value(TX6_FEC_RST_GPIO, 1);
468 ret = cpu_eth_init(bis);
470 printf("cpu_eth_init() failed: %d\n", ret);
475 static void tx6_init_mac(void)
479 imx_get_mac_from_fuse(-1, mac);
480 if (!is_valid_ether_addr(mac)) {
481 printf("No valid MAC address programmed\n");
485 printf("MAC addr from fuse: %pM\n", mac);
486 eth_setenv_enetaddr("ethaddr", mac);
489 static inline void tx6_init_mac(void)
492 #endif /* CONFIG_FEC_MXC */
500 static inline int calc_blink_rate(void)
502 if (!tx6_temp_check_enabled)
503 return CONFIG_SYS_HZ;
505 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
506 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
507 (TEMPERATURE_HOT - TEMPERATURE_MIN);
510 void show_activity(int arg)
512 static int led_state = LED_STATE_INIT;
513 static int blink_rate;
516 if (led_state == LED_STATE_INIT) {
518 gpio_set_value(TX6_LED_GPIO, 1);
519 led_state = LED_STATE_ON;
520 blink_rate = calc_blink_rate();
522 if (get_timer(last) > blink_rate) {
523 blink_rate = calc_blink_rate();
524 last = get_timer_masked();
525 if (led_state == LED_STATE_ON) {
526 gpio_set_value(TX6_LED_GPIO, 0);
528 gpio_set_value(TX6_LED_GPIO, 1);
530 led_state = 1 - led_state;
535 static const iomux_v3_cfg_t stk5_pads[] = {
536 /* SW controlled LED on STK5 baseboard */
537 MX6_PAD_EIM_A18__GPIO2_IO20,
539 /* I2C bus on DIMM pins 40/41 */
540 MX6_PAD_GPIO_6__I2C3_SDA,
541 MX6_PAD_GPIO_3__I2C3_SCL,
543 /* TSC200x PEN IRQ */
544 MX6_PAD_EIM_D26__GPIO3_IO26,
546 /* EDT-FT5x06 Polytouch panel */
547 MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
548 MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
549 MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
552 MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
553 MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
555 MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
556 MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
557 MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
560 static const struct gpio stk5_gpios[] = {
561 { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
563 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
564 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
565 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
566 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
567 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
571 static u16 tx6_cmap[256];
572 vidinfo_t panel_info = {
573 /* set to max. size supported by SoC */
577 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
581 static struct fb_videomode tx6_fb_modes[] = {
582 #ifndef CONFIG_SYS_LVDS_IF
584 /* Standard VGA timing */
589 .pixclock = KHZ2PICOS(25175),
596 .sync = FB_SYNC_CLK_LAT_FALL,
599 /* Emerging ETV570 640 x 480 display. Syncs low active,
600 * DE high active, 115.2 mm x 86.4 mm display area
601 * VGA compatible timing
607 .pixclock = KHZ2PICOS(25175),
614 .sync = FB_SYNC_CLK_LAT_FALL,
617 /* Emerging ET0350G0DH6 320 x 240 display.
618 * 70.08 mm x 52.56 mm display area.
624 .pixclock = KHZ2PICOS(6500),
625 .left_margin = 68 - 34,
628 .upper_margin = 18 - 3,
631 .sync = FB_SYNC_CLK_LAT_FALL,
634 /* Emerging ET0430G0DH6 480 x 272 display.
635 * 95.04 mm x 53.856 mm display area.
641 .pixclock = KHZ2PICOS(9000),
648 .sync = FB_SYNC_CLK_LAT_FALL,
651 /* Emerging ET0500G0DH6 800 x 480 display.
652 * 109.6 mm x 66.4 mm display area.
658 .pixclock = KHZ2PICOS(33260),
659 .left_margin = 216 - 128,
661 .right_margin = 1056 - 800 - 216,
662 .upper_margin = 35 - 2,
664 .lower_margin = 525 - 480 - 35,
665 .sync = FB_SYNC_CLK_LAT_FALL,
668 /* Emerging ETQ570G0DH6 320 x 240 display.
669 * 115.2 mm x 86.4 mm display area.
675 .pixclock = KHZ2PICOS(6400),
679 .upper_margin = 16, /* 15 according to datasheet */
680 .vsync_len = 3, /* TVP -> 1>x>5 */
681 .lower_margin = 4, /* 4.5 according to datasheet */
682 .sync = FB_SYNC_CLK_LAT_FALL,
685 /* Emerging ET0700G0DH6 800 x 480 display.
686 * 152.4 mm x 91.44 mm display area.
692 .pixclock = KHZ2PICOS(33260),
693 .left_margin = 216 - 128,
695 .right_margin = 1056 - 800 - 216,
696 .upper_margin = 35 - 2,
698 .lower_margin = 525 - 480 - 35,
699 .sync = FB_SYNC_CLK_LAT_FALL,
702 /* Emerging ET070001DM6 800 x 480 display.
703 * 152.4 mm x 91.44 mm display area.
705 .name = "ET070001DM6",
709 .pixclock = KHZ2PICOS(33260),
710 .left_margin = 216 - 128,
712 .right_margin = 1056 - 800 - 216,
713 .upper_margin = 35 - 2,
715 .lower_margin = 525 - 480 - 35,
720 /* HannStar HSD100PXN1
721 * 202.7m mm x 152.06 mm display area.
723 .name = "HSD100PXN1",
727 .pixclock = KHZ2PICOS(65000),
734 .sync = FB_SYNC_CLK_LAT_FALL,
738 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
746 .sync = FB_SYNC_CLK_LAT_FALL,
750 static int lcd_enabled = 1;
751 static int lcd_bl_polarity;
753 static int lcd_backlight_polarity(void)
755 return lcd_bl_polarity;
758 void lcd_enable(void)
761 * global variable from common/lcd.c
762 * Set to 0 here to prevent messages from going to LCD
763 * rather than serial console
767 karo_load_splashimage(1);
770 debug("Switching LCD on\n");
771 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
773 gpio_set_value(TX6_LCD_RST_GPIO, 1);
775 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
776 lcd_backlight_polarity());
780 void lcd_disable(void)
783 printf("Disabling LCD\n");
788 void lcd_panel_disable(void)
791 debug("Switching LCD off\n");
792 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
793 !lcd_backlight_polarity());
794 gpio_set_value(TX6_LCD_RST_GPIO, 0);
795 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
799 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
801 MX6_PAD_EIM_D29__GPIO3_IO29,
802 /* LCD POWER_ENABLE */
803 MX6_PAD_EIM_EB3__GPIO2_IO31,
804 /* LCD Backlight (PWM) */
805 MX6_PAD_GPIO_1__GPIO1_IO01,
807 #ifndef CONFIG_SYS_LVDS_IF
809 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
810 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
811 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
812 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
813 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
814 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
815 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
816 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
817 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
818 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
819 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
820 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
821 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
822 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
823 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
824 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
825 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
826 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
827 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
828 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
829 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
830 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
831 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
832 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
833 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
834 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
835 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
836 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
840 static const struct gpio stk5_lcd_gpios[] = {
841 { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
842 { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
843 { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
846 void lcd_ctrl_init(void *lcdbase)
848 int color_depth = 24;
849 const char *video_mode = karo_get_vmode(getenv("video_mode"));
853 struct fb_videomode *p = &tx6_fb_modes[0];
854 struct fb_videomode fb_mode;
855 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
858 unsigned long di_clk_rate = 65000000;
861 debug("LCD disabled\n");
865 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
866 debug("Disabling LCD\n");
868 setenv("splashimage", NULL);
873 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
875 if (video_mode == NULL) {
876 debug("Disabling LCD\n");
881 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
883 debug("Using video mode from FDT\n");
885 if (fb_mode.xres > panel_info.vl_col ||
886 fb_mode.yres > panel_info.vl_row) {
887 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
888 fb_mode.xres, fb_mode.yres,
889 panel_info.vl_col, panel_info.vl_row);
895 debug("Trying compiled-in video modes\n");
896 while (p->name != NULL) {
897 if (strcmp(p->name, vm) == 0) {
898 debug("Using video mode: '%s'\n", p->name);
905 debug("Trying to decode video_mode: '%s'\n", vm);
906 while (*vm != '\0') {
907 if (*vm >= '0' && *vm <= '9') {
910 val = simple_strtoul(vm, &end, 0);
913 if (val > panel_info.vl_col)
914 val = panel_info.vl_col;
916 panel_info.vl_col = val;
918 } else if (!yres_set) {
919 if (val > panel_info.vl_row)
920 val = panel_info.vl_row;
922 panel_info.vl_row = val;
924 } else if (!bpp_set) {
929 pix_fmt = IPU_PIX_FMT_LVDS888;
943 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
944 end - vm, vm, color_depth);
947 } else if (!refresh_set) {
974 if (p->xres == 0 || p->yres == 0) {
975 printf("Invalid video mode: %s\n", getenv("video_mode"));
977 printf("Supported video modes are:");
978 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
979 printf(" %s", p->name);
984 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
985 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
986 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
990 panel_info.vl_col = p->xres;
991 panel_info.vl_row = p->yres;
993 switch (color_depth) {
995 panel_info.vl_bpix = LCD_COLOR8;
998 panel_info.vl_bpix = LCD_COLOR16;
1001 panel_info.vl_bpix = LCD_COLOR32;
1004 p->pixclock = KHZ2PICOS(refresh *
1005 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1006 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1008 debug("Pixel clock set to %lu.%03lu MHz\n",
1009 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1011 if (p != &fb_mode) {
1014 debug("Creating new display-timing node from '%s'\n",
1016 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1018 printf("Failed to create new display-timing node from '%s': %d\n",
1022 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1023 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1024 ARRAY_SIZE(stk5_lcd_pads));
1026 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1027 switch (lcd_bus_width) {
1029 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1033 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1038 pix_fmt = IPU_PIX_FMT_RGB565;
1044 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1049 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1050 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1054 if (lvds_chan_mask == 0) {
1055 printf("No LVDS channel active\n");
1060 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1061 if (lcd_bus_width == 24)
1062 gpr2 |= (1 << 5) | (1 << 7);
1063 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1064 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1065 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1066 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1068 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1069 gpr3 &= ~((3 << 8) | (3 << 6));
1070 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1072 if (karo_load_splashimage(0) == 0) {
1075 debug("Initializing LCD controller\n");
1076 ret = ipuv3_fb_init(p, 0, pix_fmt,
1077 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1080 printf("Failed to initialize FB driver: %d\n", ret);
1084 debug("Skipping initialization of LCD controller\n");
1088 #define lcd_enabled 0
1089 #endif /* CONFIG_LCD */
1091 static void stk5_board_init(void)
1093 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1094 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1097 static void stk5v3_board_init(void)
1102 static void stk5v5_board_init(void)
1106 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1107 "Flexcan Transceiver");
1108 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1111 static void tx6qdl_set_cpu_clock(void)
1113 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1115 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1118 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1119 printf("%s detected; skipping cpu clock change\n",
1120 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1123 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1124 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1125 printf("CPU clock set to %lu.%03lu MHz\n",
1126 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1128 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1132 int board_late_init(void)
1135 const char *baseboard;
1139 if (tx6_temp_check_enabled)
1140 check_cpu_temperature(1);
1142 tx6qdl_set_cpu_clock();
1145 setenv_ulong("safeboot", 1);
1146 else if (wrsr & WRSR_TOUT)
1147 setenv_ulong("wdreset", 1);
1149 karo_fdt_move_fdt();
1151 baseboard = getenv("baseboard");
1155 printf("Baseboard: %s\n", baseboard);
1157 if (strncmp(baseboard, "stk5", 4) == 0) {
1158 if ((strlen(baseboard) == 4) ||
1159 strcmp(baseboard, "stk5-v3") == 0) {
1160 stk5v3_board_init();
1161 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1162 const char *otg_mode = getenv("otg_mode");
1164 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1165 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1166 otg_mode, baseboard);
1167 setenv("otg_mode", "none");
1169 stk5v5_board_init();
1171 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1175 printf("WARNING: Unsupported baseboard: '%s'\n",
1183 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1188 #ifdef CONFIG_TX6_NAND
1189 #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1191 #ifdef CONFIG_MMC_BOOT_SIZE
1192 #define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
1194 #define TX6_FLASH_SZ 2
1196 #endif /* CONFIG_TX6_NAND */
1198 #define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
1200 static char tx6_mem_table[] = {
1201 '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
1202 '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
1203 '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
1204 '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
1205 '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
1206 '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
1207 '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
1208 '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
1209 '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
1210 '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
1211 '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
1212 '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
1215 static inline char tx6_mem_suffix(void)
1217 size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1219 debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1220 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1222 if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1225 return tx6_mem_table[mem_idx];
1231 } tx6_mod_revs[] = {
1237 static int tx6_get_mod_rev(void)
1241 for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
1242 int ret = i2c_probe(tx6_mod_revs[i].addr);
1244 debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr);
1245 return tx6_mod_revs[i].rev;
1247 debug("I2C probe returned %d for addr %02x\n", ret,
1248 tx6_mod_revs[i].addr);
1253 int checkboard(void)
1255 u32 cpurev = get_cpu_rev();
1256 int cpu_variant = (cpurev >> 12) & 0xff;
1258 tx6qdl_print_cpuinfo();
1260 i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */);
1262 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1264 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1265 is_lvds(), tx6_get_mod_rev(),
1271 #ifdef CONFIG_SERIAL_TAG
1272 void get_board_serial(struct tag_serialnr *serialnr)
1274 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1275 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1277 serialnr->low = readl(&fuse->cfg0);
1278 serialnr->high = readl(&fuse->cfg1);
1282 #if defined(CONFIG_OF_BOARD_SETUP)
1283 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1284 #include <jffs2/jffs2.h>
1285 #include <mtd_node.h>
1286 static struct node_info nodes[] = {
1287 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1290 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1293 static const char *tx6_touchpanels[] = {
1299 int ft_board_setup(void *blob, bd_t *bd)
1301 const char *baseboard = getenv("baseboard");
1302 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1303 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1306 ret = fdt_increase_size(blob, 4096);
1308 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1312 karo_fdt_enable_node(blob, "stk5led", 0);
1314 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1315 fdt_fixup_ethernet(blob);
1317 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1318 ARRAY_SIZE(tx6_touchpanels));
1319 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1320 karo_fdt_fixup_flexcan(blob, stk5_v5);
1322 karo_fdt_update_fb_mode(blob, video_mode);
1326 #endif /* CONFIG_OF_BOARD_SETUP */