2 * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
39 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
43 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO IMX_GPIO_NR(3, 28)
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
50 #define TEMPERATURE_MIN (-40)
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
55 #define TEMPERATURE_HOT 80
58 DECLARE_GLOBAL_DATA_PTR;
60 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
67 #define TX6_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
71 #define TX6_FEC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
75 #define TX6_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
79 #define TX6_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
87 MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
90 #if CONFIG_MXC_UART_BASE == UART1_BASE
91 MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
92 MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
93 MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
94 MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
96 #if CONFIG_MXC_UART_BASE == UART2_BASE
97 MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
98 MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
99 MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
100 MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
102 #if CONFIG_MXC_UART_BASE == UART3_BASE
103 MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
104 MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
105 MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
106 MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
109 MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
110 MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
112 /* FEC PHY GPIO functions */
113 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
114 TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
115 MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
116 TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
117 MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
122 MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
123 MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
124 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
128 MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
129 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
130 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
131 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
132 MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
133 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
134 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
137 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
139 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
141 MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
145 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
147 MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
148 MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
151 static const struct gpio const tx6qdl_gpios[] = {
152 /* These two entries are used to forcefully reinitialize the I2C bus */
153 { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
154 { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
156 { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
157 { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
158 { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
159 { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
162 static int pmic_addr __data;
164 #if defined(TX6_I2C1_SCL_GPIO) && defined(TX6_I2C1_SDA_GPIO)
165 #define SCL_BANK (TX6_I2C1_SCL_GPIO / 32)
166 #define SDA_BANK (TX6_I2C1_SDA_GPIO / 32)
167 #define SCL_BIT (1 << (TX6_I2C1_SCL_GPIO % 32))
168 #define SDA_BIT (1 << (TX6_I2C1_SDA_GPIO % 32))
170 static void * const gpio_ports[] = {
171 (void *)GPIO1_BASE_ADDR,
172 (void *)GPIO2_BASE_ADDR,
173 (void *)GPIO3_BASE_ADDR,
174 (void *)GPIO4_BASE_ADDR,
175 (void *)GPIO5_BASE_ADDR,
176 (void *)GPIO6_BASE_ADDR,
177 (void *)GPIO7_BASE_ADDR,
180 static void tx6_i2c_recover(void)
184 struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
185 struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
187 if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
188 (readl(&sda_regs->gpio_psr) & SDA_BIT))
191 debug("Clearing I2C bus\n");
192 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
193 printf("I2C SCL stuck LOW\n");
196 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
197 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
199 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
200 ARRAY_SIZE(tx6_i2c_gpio_pads));
202 if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
203 printf("I2C SDA stuck LOW\n");
205 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
206 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
207 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
210 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
211 ARRAY_SIZE(tx6_i2c_gpio_pads));
215 for (i = 0; i < 18; i++) {
216 u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
219 (reg & SCL_BIT) ? "Sett" : "Clear");
220 writel(reg, &scl_regs->gpio_dr);
223 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
225 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
232 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
233 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
236 printf("I2C bus recovery succeeded\n");
238 printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
241 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
242 ARRAY_SIZE(tx6_i2c_pads));
247 /* placed in section '.data' to prevent overwriting relocation info
250 static u32 wrsr __data;
252 #define WRSR_POR (1 << 4)
253 #define WRSR_TOUT (1 << 1)
254 #define WRSR_SFTW (1 << 0)
256 static void print_reset_cause(void)
258 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
259 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
263 printf("Reset cause: ");
265 srsr = readl(&src_regs->srsr);
266 wrsr = readw(wdt_base + 4);
268 if (wrsr & WRSR_POR) {
269 printf("%sPOR", dlm);
272 if (srsr & 0x00004) {
273 printf("%sCSU", dlm);
276 if (srsr & 0x00008) {
277 printf("%sIPP USER", dlm);
280 if (srsr & 0x00010) {
281 if (wrsr & WRSR_SFTW) {
282 printf("%sSOFT", dlm);
285 if (wrsr & WRSR_TOUT) {
286 printf("%sWDOG", dlm);
290 if (srsr & 0x00020) {
291 printf("%sJTAG HIGH-Z", dlm);
294 if (srsr & 0x00040) {
295 printf("%sJTAG SW", dlm);
298 if (srsr & 0x10000) {
299 printf("%sWARM BOOT", dlm);
308 static const char __data *tx6_mod_suffix;
310 #ifdef CONFIG_IMX6_THERMAL
312 #include <imx_thermal.h>
315 static void print_temperature(void)
317 struct udevice *thermal_dev;
318 int cpu_tmp, minc, maxc, ret;
319 char const *grade_str;
320 static u32 __data thermal_calib;
322 puts("Temperature: ");
323 switch (get_cpu_temp_grade(&minc, &maxc)) {
324 case TEMP_AUTOMOTIVE:
325 grade_str = "Automotive";
327 case TEMP_INDUSTRIAL:
328 grade_str = "Industrial";
330 case TEMP_EXTCOMMERCIAL:
331 grade_str = "Extended Commercial";
334 grade_str = "Commercial";
336 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
337 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
339 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
342 printf(" at %dC", cpu_tmp);
344 puts(" - failed to read sensor data");
346 puts(" - no sensor device found");
349 if (fuse_read(1, 6, &thermal_calib) == 0) {
350 printf(" - calibration data 0x%08x\n", thermal_calib);
352 puts(" - Failed to read thermal calib fuse\n");
356 static inline void print_temperature(void)
363 u32 cpurev = get_cpu_rev();
366 if (is_cpu_type(MXC_CPU_MX6SL)) {
368 tx6_mod_suffix = "?";
369 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
371 tx6_mod_suffix = "U";
372 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
374 tx6_mod_suffix = "S";
375 } else if (is_cpu_type(MXC_CPU_MX6Q)) {
377 tx6_mod_suffix = "Q";
378 } else if (is_cpu_type(MXC_CPU_MX6QP)) {
380 tx6_mod_suffix = "QP";
383 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
385 (cpurev & 0x000F0) >> 4,
386 (cpurev & 0x0000F) >> 0,
387 mxc_get_clock(MXC_ARM_CLK) / 1000000);
391 #ifdef CONFIG_MX6_TEMPERATURE_HOT
392 check_cpu_temperature(1);
398 /* serial port not initialized at this point */
399 int board_early_init_f(void)
404 #ifndef CONFIG_MX6_TEMPERATURE_HOT
405 static bool tx6_temp_check_enabled = true;
407 #define tx6_temp_check_enabled 0
410 #ifdef CONFIG_TX6_NAND
411 #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
413 #ifdef CONFIG_MMC_BOOT_SIZE
414 #define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
416 #define TX6_FLASH_SZ 2
418 #endif /* CONFIG_TX6_NAND */
420 #define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
422 static char tx6_mem_table[] = {
423 '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
424 '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
425 '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
426 '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
427 '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
428 '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
429 '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
430 '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
431 '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
432 '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
433 '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
434 '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
437 #ifdef CONFIG_RN5T567
439 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
440 #define VDD_CORE_VAL rn5t_mV_to_regval(1400) /* DCDC1 */
441 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
442 #define VDD_SOC_VAL rn5t_mV_to_regval(1400) /* DCDC2 */
443 #define VDD_SOC_VAL_LP rn5t_mV_to_regval(1400)
444 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
445 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
446 #define VDD_HIGH_VAL rn5t_mV_to_regval(3000) /* DCDC4 */
447 #define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3000)
448 #define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */
449 #define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300)
450 #define VDD_IO_EXT_VAL rn5t_mV_to_regval2(3300) /* LDO2 */
451 #define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval2(3300)
453 static struct pmic_regs rn5t567_regs[] = {
454 { RN5T567_NOETIMSET, 0x5, },
455 { RN5T567_DC1DAC, VDD_CORE_VAL, },
456 { RN5T567_DC2DAC, VDD_SOC_VAL, },
457 { RN5T567_DC3DAC, VDD_DDR_VAL, },
458 { RN5T567_DC4DAC, VDD_HIGH_VAL, },
459 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
460 { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
461 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
462 { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
463 { RN5T567_DC1CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
464 { RN5T567_DC2CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
465 { RN5T567_DC3CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
466 { RN5T567_DC4CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
467 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
468 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
469 { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
470 { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
471 { RN5T567_LDOEN1, 0x03, ~0x1f, },
472 { RN5T567_LDOEN2, 0x10, ~0x30, },
473 { RN5T567_LDODIS, 0x1c, ~0x1f, },
474 { RN5T567_INTPOL, 0, },
475 { RN5T567_INTEN, 0x3, },
476 { RN5T567_DCIREN, 0xf, },
477 { RN5T567_EN_GPIR, 0, },
484 struct pmic_regs *regs;
487 #ifdef CONFIG_LTC3676
488 { 0x3c, 1, NULL, 0, },
490 #ifdef CONFIG_RN5T567
491 { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
495 static inline char tx6_mem_suffix(void)
497 size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
499 debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
500 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
502 if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
504 if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
507 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
508 return tx6_mem_table[mem_idx];
511 static int tx6_get_mod_rev(unsigned int pmic_id)
513 if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
514 return tx6_mod_revs[pmic_id].rev;
519 static int tx6_pmic_probe(void)
523 debug("%s@%d: \n", __func__, __LINE__);
525 for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
526 u8 i2c_addr = tx6_mod_revs[i].addr;
527 int ret = i2c_probe(i2c_addr);
530 debug("I2C probe succeeded for addr 0x%02x\n",
534 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
539 static int tx6_mipi(void)
541 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
542 struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
543 u32 gp1 = readl(&fuse->gp1);
545 debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
554 debug("%s@%d: \n", __func__, __LINE__);
556 pmic_id = tx6_pmic_probe();
557 if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
558 pmic_addr = tx6_mod_revs[pmic_id].addr;
560 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
562 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
563 tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
568 ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
570 printf("Failed to request tx6qdl_gpios: %d\n", ret);
572 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
574 /* Address of boot parameters */
575 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
576 gd->bd->bi_arch_number = -1;
578 if (ctrlc() || (wrsr & WRSR_TOUT)) {
579 if (wrsr & WRSR_TOUT)
580 printf("WDOG RESET detected; Skipping PMIC setup\n");
582 printf("<CTRL-C> detected; safeboot enabled\n");
583 #ifndef CONFIG_MX6_TEMPERATURE_HOT
584 tx6_temp_check_enabled = false;
589 ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
590 tx6_mod_revs[pmic_id].num_regs);
592 printf("Failed to setup PMIC voltages: %d\n", ret);
600 debug("%s@%d: \n", __func__, __LINE__);
602 /* dram_init must store complete ramsize in gd->ram_size */
603 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
604 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
608 void dram_init_banksize(void)
610 debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
611 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
612 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
613 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
615 #if CONFIG_NR_DRAM_BANKS > 1
616 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
617 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
622 #ifdef CONFIG_FSL_ESDHC
623 #define SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
624 PAD_CTL_SPEED_MED | \
625 PAD_CTL_DSE_40ohm | \
628 static const iomux_v3_cfg_t mmc0_pads[] = {
629 MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
630 MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
631 MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
632 MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
633 MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
634 MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
636 MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
639 static const iomux_v3_cfg_t mmc1_pads[] = {
640 MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
641 MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
642 MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
643 MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
644 MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
645 MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
647 MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
650 #ifdef CONFIG_TX6_EMMC
651 static const iomux_v3_cfg_t mmc3_pads[] = {
652 MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
653 MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
654 MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
655 MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
656 MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
657 MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
659 MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
663 static struct tx6_esdhc_cfg {
664 const iomux_v3_cfg_t *pads;
666 enum mxc_clock clkid;
667 struct fsl_esdhc_cfg cfg;
669 } tx6qdl_esdhc_cfg[] = {
670 #ifdef CONFIG_TX6_EMMC
673 .num_pads = ARRAY_SIZE(mmc3_pads),
674 .clkid = MXC_ESDHC4_CLK,
676 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
684 .num_pads = ARRAY_SIZE(mmc0_pads),
685 .clkid = MXC_ESDHC_CLK,
687 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
690 .cd_gpio = IMX_GPIO_NR(7, 2),
694 .num_pads = ARRAY_SIZE(mmc1_pads),
695 .clkid = MXC_ESDHC2_CLK,
697 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
700 .cd_gpio = IMX_GPIO_NR(7, 3),
704 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
706 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
709 int board_mmc_getcd(struct mmc *mmc)
711 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
713 if (cfg->cd_gpio < 0)
716 debug("SD card %d is %spresent (GPIO %d)\n",
717 cfg - tx6qdl_esdhc_cfg,
718 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
720 return !gpio_get_value(cfg->cd_gpio);
723 int board_mmc_init(bd_t *bis)
727 debug("%s@%d: \n", __func__, __LINE__);
729 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
731 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
734 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
735 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
737 if (cfg->cd_gpio >= 0) {
738 ret = gpio_request_one(cfg->cd_gpio,
739 GPIOFLAG_INPUT, "MMC CD");
741 printf("Error %d requesting GPIO%d_%d\n",
742 ret, cfg->cd_gpio / 32,
748 debug("%s: Initializing MMC slot %d\n", __func__, i);
749 fsl_esdhc_initialize(bis, &cfg->cfg);
751 mmc = find_mmc_device(i);
754 if (board_mmc_getcd(mmc))
759 #endif /* CONFIG_CMD_MMC */
761 #ifdef CONFIG_FEC_MXC
767 int board_eth_init(bd_t *bis)
771 debug("%s@%d: \n", __func__, __LINE__);
773 /* delay at least 21ms for the PHY internal POR signal to deassert */
776 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
777 ARRAY_SIZE(tx6qdl_fec_pads));
779 /* Deassert RESET to the external phy */
780 gpio_set_value(TX6_FEC_RST_GPIO, 1);
782 ret = cpu_eth_init(bis);
784 printf("cpu_eth_init() failed: %d\n", ret);
789 static void tx6_init_mac(void)
793 imx_get_mac_from_fuse(0, mac);
794 if (!is_valid_ethaddr(mac)) {
795 printf("No valid MAC address programmed\n");
799 printf("MAC addr from fuse: %pM\n", mac);
800 eth_setenv_enetaddr("ethaddr", mac);
803 static inline void tx6_init_mac(void)
806 #endif /* CONFIG_FEC_MXC */
815 static int led_state = LED_STATE_INIT;
817 static inline int calc_blink_rate(void)
819 if (!tx6_temp_check_enabled)
820 return CONFIG_SYS_HZ;
822 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
823 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
824 (TEMPERATURE_HOT - TEMPERATURE_MIN);
827 void show_activity(int arg)
829 static int blink_rate;
833 if (led_state == LED_STATE_INIT) {
835 ret = gpio_set_value(TX6_LED_GPIO, 1);
837 led_state = LED_STATE_DISABLED;
840 led_state = LED_STATE_ON;
841 blink_rate = calc_blink_rate();
842 } else if (led_state != LED_STATE_DISABLED) {
843 if (get_timer(last) > blink_rate) {
844 blink_rate = calc_blink_rate();
845 last = get_timer_masked();
846 if (led_state == LED_STATE_ON) {
847 gpio_set_value(TX6_LED_GPIO, 0);
849 gpio_set_value(TX6_LED_GPIO, 1);
851 led_state = 1 - led_state;
856 static const iomux_v3_cfg_t stk5_pads[] = {
857 /* SW controlled LED on STK5 baseboard */
858 MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
860 /* I2C bus on DIMM pins 40/41 */
861 MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
862 MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
864 /* TSC200x PEN IRQ */
865 MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
867 /* EDT-FT5x06 Polytouch panel */
868 MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
869 MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
870 MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
873 MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
874 MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
876 MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
877 MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
878 MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
881 static const struct gpio stk5_gpios[] = {
882 { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
884 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
885 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
886 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
887 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
888 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
892 vidinfo_t panel_info = {
893 /* set to max. size supported by SoC */
897 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
900 static struct fb_videomode tx6_fb_modes[] = {
902 /* Standard VGA timing */
907 .pixclock = KHZ2PICOS(25175),
914 .sync = FB_SYNC_CLK_LAT_FALL,
917 /* Emerging ETV570 640 x 480 display. Syncs low active,
918 * DE high active, 115.2 mm x 86.4 mm display area
919 * VGA compatible timing
925 .pixclock = KHZ2PICOS(25175),
932 .sync = FB_SYNC_CLK_LAT_FALL,
935 /* Emerging ETM0700G0DH6 800 x 480 display.
936 * 152.4 mm x 91.44 mm display area.
942 .pixclock = KHZ2PICOS(33260),
949 .sync = FB_SYNC_CLK_LAT_FALL,
951 #ifndef CONFIG_SYS_LVDS_IF
953 /* Emerging ET0350G0DH6 320 x 240 display.
954 * 70.08 mm x 52.56 mm display area.
960 .pixclock = KHZ2PICOS(6500),
967 .sync = FB_SYNC_CLK_LAT_FALL,
970 /* Emerging ET0430G0DH6 480 x 272 display.
971 * 95.04 mm x 53.856 mm display area.
977 .pixclock = KHZ2PICOS(9000),
986 /* Emerging ET0500G0DH6 800 x 480 display.
987 * 109.6 mm x 66.4 mm display area.
993 .pixclock = KHZ2PICOS(33260),
1000 .sync = FB_SYNC_CLK_LAT_FALL,
1003 /* Emerging ETQ570G0DH6 320 x 240 display.
1004 * 115.2 mm x 86.4 mm display area.
1010 .pixclock = KHZ2PICOS(6400),
1014 .upper_margin = 16, /* 15 according to datasheet */
1015 .vsync_len = 3, /* TVP -> 1>x>5 */
1016 .lower_margin = 4, /* 4.5 according to datasheet */
1017 .sync = FB_SYNC_CLK_LAT_FALL,
1021 /* HannStar HSD100PXN1
1022 * 202.7m mm x 152.06 mm display area.
1024 .name = "HSD100PXN1",
1028 .pixclock = KHZ2PICOS(65000),
1031 .right_margin = 320,
1035 .sync = FB_SYNC_CLK_LAT_FALL,
1039 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1047 .sync = FB_SYNC_CLK_LAT_FALL,
1051 static int lcd_enabled = 1;
1052 static int lcd_bl_polarity;
1054 static int lcd_backlight_polarity(void)
1056 return lcd_bl_polarity;
1059 void lcd_enable(void)
1062 * global variable from common/lcd.c
1063 * Set to 0 here to prevent messages from going to LCD
1064 * rather than serial console
1069 karo_load_splashimage(1);
1071 debug("Switching LCD on\n");
1072 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1074 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1076 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1077 lcd_backlight_polarity());
1081 void lcd_disable(void)
1084 printf("Disabling LCD\n");
1085 ipuv3_fb_shutdown();
1089 void lcd_panel_disable(void)
1092 debug("Switching LCD off\n");
1093 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1094 !lcd_backlight_polarity());
1095 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1096 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1100 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1102 MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1103 /* LCD POWER_ENABLE */
1104 MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1105 /* LCD Backlight (PWM) */
1106 MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1108 #ifndef CONFIG_SYS_LVDS_IF
1110 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1111 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1112 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1113 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1114 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1115 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1116 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1117 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1118 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1119 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1120 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1121 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1122 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1123 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1124 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1125 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1126 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1127 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1128 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1129 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1130 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1131 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1132 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1133 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1134 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1135 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1136 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1137 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1141 static const struct gpio stk5_lcd_gpios[] = {
1142 { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1143 { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1144 { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1147 void lcd_ctrl_init(void *lcdbase)
1149 int color_depth = 24;
1150 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1154 struct fb_videomode *p = &tx6_fb_modes[0];
1155 struct fb_videomode fb_mode;
1156 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1159 unsigned long di_clk_rate = 65000000;
1162 debug("LCD disabled\n");
1166 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1167 debug("Disabling LCD\n");
1169 setenv("splashimage", NULL);
1173 karo_fdt_move_fdt();
1174 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1176 if (video_mode == NULL) {
1177 debug("Disabling LCD\n");
1182 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1184 debug("Using video mode from FDT\n");
1186 if (fb_mode.xres > panel_info.vl_col ||
1187 fb_mode.yres > panel_info.vl_row) {
1188 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1189 fb_mode.xres, fb_mode.yres,
1190 panel_info.vl_col, panel_info.vl_row);
1195 if (p->name != NULL)
1196 debug("Trying compiled-in video modes\n");
1197 while (p->name != NULL) {
1198 if (strcmp(p->name, vm) == 0) {
1199 debug("Using video mode: '%s'\n", p->name);
1206 debug("Trying to decode video_mode: '%s'\n", vm);
1207 while (*vm != '\0') {
1208 if (*vm >= '0' && *vm <= '9') {
1211 val = simple_strtoul(vm, &end, 0);
1214 if (val > panel_info.vl_col)
1215 val = panel_info.vl_col;
1217 panel_info.vl_col = val;
1219 } else if (!yres_set) {
1220 if (val > panel_info.vl_row)
1221 val = panel_info.vl_row;
1223 panel_info.vl_row = val;
1225 } else if (!bpp_set) {
1230 pix_fmt = IPU_PIX_FMT_LVDS888;
1244 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1249 } else if (!refresh_set) {
1276 if (p->xres == 0 || p->yres == 0) {
1277 printf("Invalid video mode: %s\n", getenv("video_mode"));
1279 printf("Supported video modes are:");
1280 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1281 printf(" %s", p->name);
1286 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1287 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1288 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1292 panel_info.vl_col = p->xres;
1293 panel_info.vl_row = p->yres;
1295 switch (color_depth) {
1297 panel_info.vl_bpix = LCD_COLOR8;
1300 panel_info.vl_bpix = LCD_COLOR16;
1303 panel_info.vl_bpix = LCD_COLOR32;
1306 if (refresh_set || p->pixclock == 0)
1307 p->pixclock = KHZ2PICOS(refresh *
1308 (p->xres + p->left_margin +
1309 p->right_margin + p->hsync_len) *
1310 (p->yres + p->upper_margin +
1311 p->lower_margin + p->vsync_len) /
1313 debug("Pixel clock set to %lu.%03lu MHz\n",
1314 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1316 if (p != &fb_mode) {
1319 debug("Creating new display-timing node from '%s'\n",
1321 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1323 printf("Failed to create new display-timing node from '%s': %d\n",
1327 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1328 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1329 ARRAY_SIZE(stk5_lcd_pads));
1331 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1332 switch (lcd_bus_width) {
1334 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1338 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1343 pix_fmt = IPU_PIX_FMT_RGB565;
1349 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1354 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1355 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1359 if (lvds_chan_mask == 0) {
1360 printf("No LVDS channel active\n");
1365 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1366 if (lcd_bus_width == 24)
1367 gpr2 |= (1 << 5) | (1 << 7);
1368 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1369 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1370 debug("writing %08x to GPR2[%08x]\n", gpr2,
1371 IOMUXC_BASE_ADDR + 8);
1372 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1374 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1375 gpr3 &= ~((3 << 8) | (3 << 6));
1376 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1378 if (karo_load_splashimage(0) == 0) {
1381 debug("Initializing LCD controller\n");
1382 ret = ipuv3_fb_init(p, 0, pix_fmt,
1383 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1386 printf("Failed to initialize FB driver: %d\n", ret);
1390 debug("Skipping initialization of LCD controller\n");
1396 panel_info.vl_col = 0;
1397 panel_info.vl_row = 0;
1400 #define lcd_enabled 0
1401 #endif /* CONFIG_LCD */
1403 static void stk5_board_init(void)
1407 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1409 printf("Failed to request stk5_gpios: %d\n", ret);
1412 led_state = LED_STATE_INIT;
1413 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1416 static void stk5v3_board_init(void)
1421 static void stk5v5_board_init(void)
1427 ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1428 "Flexcan Transceiver");
1430 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1434 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1438 static void tx6qdl_set_cpu_clock(void)
1440 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1442 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1445 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1446 printf("%s detected; skipping cpu clock change\n",
1447 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1450 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1451 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1452 printf("CPU clock set to %lu.%03lu MHz\n",
1453 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1455 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1459 int board_late_init(void)
1461 const char *baseboard;
1463 debug("%s@%d: \n", __func__, __LINE__);
1467 if (tx6_temp_check_enabled)
1468 check_cpu_temperature(1);
1470 tx6qdl_set_cpu_clock();
1473 setenv_ulong("safeboot", 1);
1474 else if (wrsr & WRSR_TOUT)
1475 setenv_ulong("wdreset", 1);
1477 karo_fdt_move_fdt();
1479 baseboard = getenv("baseboard");
1483 printf("Baseboard: %s\n", baseboard);
1485 if (strncmp(baseboard, "stk5", 4) == 0) {
1486 if ((strlen(baseboard) == 4) ||
1487 strcmp(baseboard, "stk5-v3") == 0) {
1488 stk5v3_board_init();
1489 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1490 const char *otg_mode = getenv("otg_mode");
1492 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1493 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1494 otg_mode, baseboard);
1495 setenv("otg_mode", "none");
1497 stk5v5_board_init();
1499 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1503 printf("WARNING: Unsupported baseboard: '%s'\n",
1512 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1517 #ifdef CONFIG_SERIAL_TAG
1518 void get_board_serial(struct tag_serialnr *serialnr)
1520 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1521 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1523 serialnr->low = readl(&fuse->cfg0);
1524 serialnr->high = readl(&fuse->cfg1);
1528 #if defined(CONFIG_OF_BOARD_SETUP)
1529 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1530 #include <jffs2/jffs2.h>
1531 #include <mtd_node.h>
1532 static struct node_info nodes[] = {
1533 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1536 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1539 static const char *tx6_touchpanels[] = {
1545 int ft_board_setup(void *blob, bd_t *bd)
1547 const char *baseboard = getenv("baseboard");
1548 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1549 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1552 ret = fdt_increase_size(blob, 4096);
1554 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1558 karo_fdt_enable_node(blob, "stk5led", 0);
1560 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1562 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1563 ARRAY_SIZE(tx6_touchpanels));
1564 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1565 karo_fdt_fixup_flexcan(blob, stk5_v5);
1567 #ifdef CONFIG_SYS_LVDS_IF
1568 karo_fdt_update_fb_mode(blob, video_mode, "/lvds0-panel");
1569 karo_fdt_update_fb_mode(blob, video_mode, "/lvds1-panel");
1571 karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1575 #endif /* CONFIG_OF_BOARD_SETUP */