2 * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
21 #include <fdt_support.h>
25 #include <fsl_esdhc.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
39 #include "../common/karo.h"
42 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
43 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
44 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
45 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
47 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
48 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
49 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
51 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
53 #ifdef CONFIG_MX6_TEMPERATURE_MIN
54 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
56 #define TEMPERATURE_MIN (-40)
58 #ifdef CONFIG_MX6_TEMPERATURE_HOT
59 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
61 #define TEMPERATURE_HOT 80
64 DECLARE_GLOBAL_DATA_PTR;
66 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
68 static const iomux_v3_cfg_t tx6qdl_pads[] = {
69 #ifndef CONFIG_NO_NAND
71 MX6_PAD_NANDF_CLE__RAWNAND_CLE,
72 MX6_PAD_NANDF_ALE__RAWNAND_ALE,
73 MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
74 MX6_PAD_NANDF_RB0__RAWNAND_READY0,
75 MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
76 MX6_PAD_SD4_CMD__RAWNAND_RDN,
77 MX6_PAD_SD4_CLK__RAWNAND_WRN,
78 MX6_PAD_NANDF_D0__RAWNAND_D0,
79 MX6_PAD_NANDF_D1__RAWNAND_D1,
80 MX6_PAD_NANDF_D2__RAWNAND_D2,
81 MX6_PAD_NANDF_D3__RAWNAND_D3,
82 MX6_PAD_NANDF_D4__RAWNAND_D4,
83 MX6_PAD_NANDF_D5__RAWNAND_D5,
84 MX6_PAD_NANDF_D6__RAWNAND_D6,
85 MX6_PAD_NANDF_D7__RAWNAND_D7,
88 MX6_PAD_GPIO_17__GPIO_7_12,
91 #if CONFIG_MXC_UART_BASE == UART1_BASE
92 MX6_PAD_SD3_DAT7__UART1_TXD,
93 MX6_PAD_SD3_DAT6__UART1_RXD,
94 MX6_PAD_SD3_DAT1__UART1_RTS,
95 MX6_PAD_SD3_DAT0__UART1_CTS,
97 #if CONFIG_MXC_UART_BASE == UART2_BASE
98 MX6_PAD_SD4_DAT4__UART2_RXD,
99 MX6_PAD_SD4_DAT7__UART2_TXD,
100 MX6_PAD_SD4_DAT5__UART2_RTS,
101 MX6_PAD_SD4_DAT6__UART2_CTS,
103 #if CONFIG_MXC_UART_BASE == UART3_BASE
104 MX6_PAD_EIM_D24__UART3_TXD,
105 MX6_PAD_EIM_D25__UART3_RXD,
106 MX6_PAD_SD3_RST__UART3_RTS,
107 MX6_PAD_SD3_DAT3__UART3_CTS,
110 MX6_PAD_EIM_D28__I2C1_SDA,
111 MX6_PAD_EIM_D21__I2C1_SCL,
113 /* FEC PHY GPIO functions */
114 MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
115 MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
116 MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
119 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
121 MX6_PAD_ENET_MDC__ENET_MDC,
122 MX6_PAD_ENET_MDIO__ENET_MDIO,
123 MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
124 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
125 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
126 MX6_PAD_ENET_RXD1__ENET_RDATA_1,
127 MX6_PAD_ENET_RXD0__ENET_RDATA_0,
128 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
129 MX6_PAD_ENET_TXD1__ENET_TDATA_1,
130 MX6_PAD_ENET_TXD0__ENET_TDATA_0,
133 static const struct gpio tx6qdl_gpios[] = {
134 { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
135 { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
136 { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
137 { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
143 /* placed in section '.data' to prevent overwriting relocation info
146 static u32 wrsr __attribute__((section(".data")));
148 #define WRSR_POR (1 << 4)
149 #define WRSR_TOUT (1 << 1)
150 #define WRSR_SFTW (1 << 0)
152 static void print_reset_cause(void)
154 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
155 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
159 printf("Reset cause: ");
161 srsr = readl(&src_regs->srsr);
162 wrsr = readw(wdt_base + 4);
164 if (wrsr & WRSR_POR) {
165 printf("%sPOR", dlm);
168 if (srsr & 0x00004) {
169 printf("%sCSU", dlm);
172 if (srsr & 0x00008) {
173 printf("%sIPP USER", dlm);
176 if (srsr & 0x00010) {
177 if (wrsr & WRSR_SFTW) {
178 printf("%sSOFT", dlm);
181 if (wrsr & WRSR_TOUT) {
182 printf("%sWDOG", dlm);
186 if (srsr & 0x00020) {
187 printf("%sJTAG HIGH-Z", dlm);
190 if (srsr & 0x00040) {
191 printf("%sJTAG SW", dlm);
194 if (srsr & 0x10000) {
195 printf("%sWARM BOOT", dlm);
204 static const char *tx6_mod_suffix;
206 static void tx6qdl_print_cpuinfo(void)
208 u32 cpurev = get_cpu_rev();
211 switch ((cpurev >> 12) & 0xff) {
214 tx6_mod_suffix = "?";
218 tx6_mod_suffix = "U";
220 case MXC_CPU_MX6SOLO:
222 tx6_mod_suffix = "S";
226 tx6_mod_suffix = "Q";
230 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
232 (cpurev & 0x000F0) >> 4,
233 (cpurev & 0x0000F) >> 0,
234 mxc_get_clock(MXC_ARM_CLK) / 1000000);
237 #ifdef CONFIG_MX6_TEMPERATURE_HOT
238 check_cpu_temperature(1);
242 int board_early_init_f(void)
244 gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
245 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
250 #ifndef CONFIG_MX6_TEMPERATURE_HOT
251 static bool tx6_temp_check_enabled = true;
253 #define tx6_temp_check_enabled 0
260 /* Address of boot parameters */
261 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
262 gd->bd->bi_arch_number = -1;
265 #ifndef CONFIG_MX6_TEMPERATURE_HOT
266 tx6_temp_check_enabled = false;
268 printf("CTRL-C detected; Skipping PMIC setup\n");
272 ret = setup_pmic_voltages();
274 printf("Failed to setup PMIC voltages\n");
282 /* dram_init must store complete ramsize in gd->ram_size */
283 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
288 void dram_init_banksize(void)
290 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
291 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
293 #if CONFIG_NR_DRAM_BANKS > 1
294 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
295 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
300 #ifdef CONFIG_CMD_MMC
301 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
302 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
303 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
305 static const iomux_v3_cfg_t mmc0_pads[] = {
306 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
307 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
308 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
309 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
310 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
311 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
313 MX6_PAD_SD3_CMD__GPIO_7_2,
316 static const iomux_v3_cfg_t mmc1_pads[] = {
317 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
318 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
319 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
320 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
321 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
322 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
324 MX6_PAD_SD3_CLK__GPIO_7_3,
327 #ifdef CONFIG_MMC_BOOT_SIZE
328 static const iomux_v3_cfg_t mmc3_pads[] = {
329 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
330 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
331 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
332 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
333 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
334 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
336 MX6_PAD_NANDF_ALE__USDHC4_RST,
340 static struct tx6_esdhc_cfg {
341 const iomux_v3_cfg_t *pads;
343 enum mxc_clock clkid;
344 struct fsl_esdhc_cfg cfg;
346 } tx6qdl_esdhc_cfg[] = {
347 #ifdef CONFIG_MMC_BOOT_SIZE
350 .num_pads = ARRAY_SIZE(mmc3_pads),
351 .clkid = MXC_ESDHC4_CLK,
353 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
361 .num_pads = ARRAY_SIZE(mmc0_pads),
362 .clkid = MXC_ESDHC_CLK,
364 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
367 .cd_gpio = IMX_GPIO_NR(7, 2),
371 .num_pads = ARRAY_SIZE(mmc1_pads),
372 .clkid = MXC_ESDHC2_CLK,
374 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
377 .cd_gpio = IMX_GPIO_NR(7, 3),
381 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
383 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
386 int board_mmc_getcd(struct mmc *mmc)
388 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
390 if (cfg->cd_gpio < 0)
393 debug("SD card %d is %spresent\n",
394 cfg - tx6qdl_esdhc_cfg,
395 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
396 return !gpio_get_value(cfg->cd_gpio);
399 int board_mmc_init(bd_t *bis)
403 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
405 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
408 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
409 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
411 if (cfg->cd_gpio >= 0) {
412 ret = gpio_request_one(cfg->cd_gpio,
413 GPIOF_INPUT, "MMC CD");
415 printf("Error %d requesting GPIO%d_%d\n",
416 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
421 debug("%s: Initializing MMC slot %d\n", __func__, i);
422 fsl_esdhc_initialize(bis, &cfg->cfg);
424 mmc = find_mmc_device(i);
427 if (board_mmc_getcd(mmc))
432 #endif /* CONFIG_CMD_MMC */
434 #ifdef CONFIG_FEC_MXC
436 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
438 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
439 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
445 int board_eth_init(bd_t *bis)
449 /* delay at least 21ms for the PHY internal POR signal to deassert */
452 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
454 /* Deassert RESET to the external phy */
455 gpio_set_value(TX6_FEC_RST_GPIO, 1);
457 ret = cpu_eth_init(bis);
459 printf("cpu_eth_init() failed: %d\n", ret);
463 #endif /* CONFIG_FEC_MXC */
471 static inline int calc_blink_rate(void)
473 if (!tx6_temp_check_enabled)
474 return CONFIG_SYS_HZ;
476 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
477 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
478 (TEMPERATURE_HOT - TEMPERATURE_MIN);
481 void show_activity(int arg)
483 static int led_state = LED_STATE_INIT;
484 static int blink_rate;
487 if (led_state == LED_STATE_INIT) {
489 gpio_set_value(TX6_LED_GPIO, 1);
490 led_state = LED_STATE_ON;
491 blink_rate = calc_blink_rate();
493 if (get_timer(last) > blink_rate) {
494 blink_rate = calc_blink_rate();
495 last = get_timer_masked();
496 if (led_state == LED_STATE_ON) {
497 gpio_set_value(TX6_LED_GPIO, 0);
499 gpio_set_value(TX6_LED_GPIO, 1);
501 led_state = 1 - led_state;
506 static const iomux_v3_cfg_t stk5_pads[] = {
507 /* SW controlled LED on STK5 baseboard */
508 MX6_PAD_EIM_A18__GPIO_2_20,
510 /* I2C bus on DIMM pins 40/41 */
511 MX6_PAD_GPIO_6__I2C3_SDA,
512 MX6_PAD_GPIO_3__I2C3_SCL,
514 /* TSC200x PEN IRQ */
515 MX6_PAD_EIM_D26__GPIO_3_26,
517 /* EDT-FT5x06 Polytouch panel */
518 MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
519 MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
520 MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
523 MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
524 MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
526 MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
527 MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
528 MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
531 static const struct gpio stk5_gpios[] = {
532 { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
534 { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
535 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
536 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
537 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
538 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
542 static u16 tx6_cmap[256];
543 vidinfo_t panel_info = {
544 /* set to max. size supported by SoC */
548 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
552 static struct fb_videomode tx6_fb_modes[] = {
553 #ifndef CONFIG_SYS_LVDS_IF
555 /* Standard VGA timing */
560 .pixclock = KHZ2PICOS(25175),
567 .sync = FB_SYNC_CLK_LAT_FALL,
570 /* Emerging ETV570 640 x 480 display. Syncs low active,
571 * DE high active, 115.2 mm x 86.4 mm display area
572 * VGA compatible timing
578 .pixclock = KHZ2PICOS(25175),
585 .sync = FB_SYNC_CLK_LAT_FALL,
588 /* Emerging ET0350G0DH6 320 x 240 display.
589 * 70.08 mm x 52.56 mm display area.
595 .pixclock = KHZ2PICOS(6500),
596 .left_margin = 68 - 34,
599 .upper_margin = 18 - 3,
602 .sync = FB_SYNC_CLK_LAT_FALL,
605 /* Emerging ET0430G0DH6 480 x 272 display.
606 * 95.04 mm x 53.856 mm display area.
612 .pixclock = KHZ2PICOS(9000),
619 .sync = FB_SYNC_CLK_LAT_FALL,
622 /* Emerging ET0500G0DH6 800 x 480 display.
623 * 109.6 mm x 66.4 mm display area.
629 .pixclock = KHZ2PICOS(33260),
630 .left_margin = 216 - 128,
632 .right_margin = 1056 - 800 - 216,
633 .upper_margin = 35 - 2,
635 .lower_margin = 525 - 480 - 35,
636 .sync = FB_SYNC_CLK_LAT_FALL,
639 /* Emerging ETQ570G0DH6 320 x 240 display.
640 * 115.2 mm x 86.4 mm display area.
646 .pixclock = KHZ2PICOS(6400),
650 .upper_margin = 16, /* 15 according to datasheet */
651 .vsync_len = 3, /* TVP -> 1>x>5 */
652 .lower_margin = 4, /* 4.5 according to datasheet */
653 .sync = FB_SYNC_CLK_LAT_FALL,
656 /* Emerging ET0700G0DH6 800 x 480 display.
657 * 152.4 mm x 91.44 mm display area.
663 .pixclock = KHZ2PICOS(33260),
664 .left_margin = 216 - 128,
666 .right_margin = 1056 - 800 - 216,
667 .upper_margin = 35 - 2,
669 .lower_margin = 525 - 480 - 35,
670 .sync = FB_SYNC_CLK_LAT_FALL,
673 /* Emerging ET070001DM6 800 x 480 display.
674 * 152.4 mm x 91.44 mm display area.
676 .name = "ET070001DM6",
680 .pixclock = KHZ2PICOS(33260),
681 .left_margin = 216 - 128,
683 .right_margin = 1056 - 800 - 216,
684 .upper_margin = 35 - 2,
686 .lower_margin = 525 - 480 - 35,
691 /* HannStar HSD100PXN1
692 * 202.7m mm x 152.06 mm display area.
694 .name = "HSD100PXN1",
698 .pixclock = KHZ2PICOS(65000),
705 .sync = FB_SYNC_CLK_LAT_FALL,
709 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
717 .sync = FB_SYNC_CLK_LAT_FALL,
721 static int lcd_enabled = 1;
722 static int lcd_bl_polarity;
724 static int lcd_backlight_polarity(void)
726 return lcd_bl_polarity;
729 void lcd_enable(void)
732 * global variable from common/lcd.c
733 * Set to 0 here to prevent messages from going to LCD
734 * rather than serial console
738 karo_load_splashimage(1);
741 debug("Switching LCD on\n");
742 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
744 gpio_set_value(TX6_LCD_RST_GPIO, 1);
746 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
747 lcd_backlight_polarity());
751 void lcd_disable(void)
754 printf("Disabling LCD\n");
759 void lcd_panel_disable(void)
762 debug("Switching LCD off\n");
763 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
764 !lcd_backlight_polarity());
765 gpio_set_value(TX6_LCD_RST_GPIO, 0);
766 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
770 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
772 MX6_PAD_EIM_D29__GPIO_3_29,
773 /* LCD POWER_ENABLE */
774 MX6_PAD_EIM_EB3__GPIO_2_31,
775 /* LCD Backlight (PWM) */
776 MX6_PAD_GPIO_1__GPIO_1_1,
778 #ifndef CONFIG_SYS_LVDS_IF
780 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
781 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
782 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
783 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
784 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
785 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
786 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
787 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
788 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
789 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
790 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
791 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
792 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
793 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
794 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
795 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
796 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
797 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
798 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
799 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
800 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
801 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
802 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
803 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
804 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
805 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
806 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
807 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
811 static const struct gpio stk5_lcd_gpios[] = {
812 { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
813 { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
814 { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
817 void lcd_ctrl_init(void *lcdbase)
819 int color_depth = 24;
820 const char *video_mode = karo_get_vmode(getenv("video_mode"));
824 struct fb_videomode *p = &tx6_fb_modes[0];
825 struct fb_videomode fb_mode;
826 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
829 unsigned long di_clk_rate = 65000000;
832 debug("LCD disabled\n");
836 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
837 debug("Disabling LCD\n");
839 setenv("splashimage", NULL);
844 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
846 if (video_mode == NULL) {
847 debug("Disabling LCD\n");
852 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
854 debug("Using video mode from FDT\n");
856 if (fb_mode.xres > panel_info.vl_col ||
857 fb_mode.yres > panel_info.vl_row) {
858 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
859 fb_mode.xres, fb_mode.yres,
860 panel_info.vl_col, panel_info.vl_row);
866 debug("Trying compiled-in video modes\n");
867 while (p->name != NULL) {
868 if (strcmp(p->name, vm) == 0) {
869 debug("Using video mode: '%s'\n", p->name);
876 debug("Trying to decode video_mode: '%s'\n", vm);
877 while (*vm != '\0') {
878 if (*vm >= '0' && *vm <= '9') {
881 val = simple_strtoul(vm, &end, 0);
884 if (val > panel_info.vl_col)
885 val = panel_info.vl_col;
887 panel_info.vl_col = val;
889 } else if (!yres_set) {
890 if (val > panel_info.vl_row)
891 val = panel_info.vl_row;
893 panel_info.vl_row = val;
895 } else if (!bpp_set) {
900 pix_fmt = IPU_PIX_FMT_LVDS888;
914 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
915 end - vm, vm, color_depth);
918 } else if (!refresh_set) {
945 if (p->xres == 0 || p->yres == 0) {
946 printf("Invalid video mode: %s\n", getenv("video_mode"));
948 printf("Supported video modes are:");
949 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
950 printf(" %s", p->name);
955 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
956 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
957 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
961 panel_info.vl_col = p->xres;
962 panel_info.vl_row = p->yres;
964 switch (color_depth) {
966 panel_info.vl_bpix = LCD_COLOR8;
969 panel_info.vl_bpix = LCD_COLOR16;
972 panel_info.vl_bpix = LCD_COLOR24;
975 p->pixclock = KHZ2PICOS(refresh *
976 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
977 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
979 debug("Pixel clock set to %lu.%03lu MHz\n",
980 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
985 debug("Creating new display-timing node from '%s'\n",
987 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
989 printf("Failed to create new display-timing node from '%s': %d\n",
993 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
994 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
995 ARRAY_SIZE(stk5_lcd_pads));
997 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
998 switch (lcd_bus_width) {
1000 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1004 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1009 pix_fmt = IPU_PIX_FMT_RGB565;
1015 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1020 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1021 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1024 if (lvds_chan_mask == 0) {
1025 printf("No LVDS channel active\n");
1030 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1031 if (lcd_bus_width == 24)
1032 gpr2 |= (1 << 5) | (1 << 7);
1033 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1034 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1035 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1036 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1038 if (karo_load_splashimage(0) == 0) {
1041 debug("Initializing LCD controller\n");
1042 ret = ipuv3_fb_init(p, 0, pix_fmt,
1043 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1046 printf("Failed to initialize FB driver: %d\n", ret);
1050 debug("Skipping initialization of LCD controller\n");
1054 #define lcd_enabled 0
1055 #endif /* CONFIG_LCD */
1057 static void stk5_board_init(void)
1059 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1060 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1063 static void stk5v3_board_init(void)
1068 static void stk5v5_board_init(void)
1072 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1073 "Flexcan Transceiver");
1074 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1077 static void tx6qdl_set_cpu_clock(void)
1079 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1081 if (had_ctrlc() || (wrsr & WRSR_TOUT))
1084 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1087 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1088 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1089 printf("CPU clock set to %lu.%03lu MHz\n",
1090 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1092 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1096 static void tx6_init_mac(void)
1100 imx_get_mac_from_fuse(-1, mac);
1101 if (!is_valid_ether_addr(mac)) {
1102 printf("No valid MAC address programmed\n");
1106 printf("MAC addr from fuse: %pM\n", mac);
1107 eth_setenv_enetaddr("ethaddr", mac);
1110 int board_late_init(void)
1113 const char *baseboard;
1115 if (tx6_temp_check_enabled)
1116 check_cpu_temperature(1);
1118 tx6qdl_set_cpu_clock();
1120 karo_fdt_move_fdt();
1122 baseboard = getenv("baseboard");
1126 printf("Baseboard: %s\n", baseboard);
1128 if (strncmp(baseboard, "stk5", 4) == 0) {
1129 if ((strlen(baseboard) == 4) ||
1130 strcmp(baseboard, "stk5-v3") == 0) {
1131 stk5v3_board_init();
1132 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1133 const char *otg_mode = getenv("otg_mode");
1135 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1136 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1137 otg_mode, baseboard);
1138 setenv("otg_mode", "none");
1140 stk5v5_board_init();
1142 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1146 printf("WARNING: Unsupported baseboard: '%s'\n",
1154 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1159 #ifdef CONFIG_NO_NAND
1160 #ifdef CONFIG_MMC_BOOT_SIZE
1161 #define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 1024 - 1 + 2)
1163 #define TX6_FLASH_SZ 3
1165 #else /* CONFIG_NO_NAND */
1166 #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1167 #endif /* CONFIG_NO_NAND */
1169 #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
1170 #define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
1172 #define TX6_DDR_SZ 2
1175 #if CONFIG_TX6_REV >= 0x3
1176 static char tx6_mem_table[] = {
1177 '4', /* 256MiB SDRAM; 128MiB NAND */
1178 '1', /* 512MiB SDRAM; 128MiB NAND */
1179 '0', /* 1GiB SDRAM; 128MiB NAND */
1180 '?', /* 256MiB SDRAM; 256MiB NAND */
1181 '?', /* 512MiB SDRAM; 256MiB NAND */
1182 '2', /* 1GiB SDRAM; 256MiB NAND */
1183 '?', /* 256MiB SDRAM; 4GiB eMMC */
1184 '5', /* 512MiB SDRAM; 4GiB eMMC */
1185 '3', /* 1GiB SDRAM; 4GiB eMMC */
1186 '?', /* 256MiB SDRAM; 8GiB eMMC */
1187 '?', /* 512MiB SDRAM; 8GiB eMMC */
1188 '?', /* 1GiB SDRAM; 8GiB eMMC */
1191 static inline char tx6_mem_suffix(void)
1193 size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1195 debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1196 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1198 if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1201 return tx6_mem_table[mem_idx];
1203 #else /* CONFIG_TX6_REV >= 0x3 */
1204 static inline char tx6_mem_suffix(void)
1206 #ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
1207 if (CONFIG_SYS_SDRAM_BUS_WIDTH == 32)
1210 #ifdef CONFIG_SYS_NAND_BLOCKS
1211 if (CONFIG_SYS_NAND_BLOCKS == 2048)
1216 #endif /* CONFIG_TX6_REV >= 0x3 */
1218 int checkboard(void)
1220 u32 cpurev = get_cpu_rev();
1221 int cpu_variant = (cpurev >> 12) & 0xff;
1223 tx6qdl_print_cpuinfo();
1225 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1227 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1228 is_lvds(), CONFIG_TX6_REV,
1234 #ifdef CONFIG_SERIAL_TAG
1235 void get_board_serial(struct tag_serialnr *serialnr)
1237 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1238 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1240 serialnr->low = readl(&fuse->cfg0);
1241 serialnr->high = readl(&fuse->cfg1);
1245 #if defined(CONFIG_OF_BOARD_SETUP)
1246 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1247 #include <jffs2/jffs2.h>
1248 #include <mtd_node.h>
1249 static struct node_info nodes[] = {
1250 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1253 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1256 static const char *tx6_touchpanels[] = {
1262 void ft_board_setup(void *blob, bd_t *bd)
1264 const char *baseboard = getenv("baseboard");
1265 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1266 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1269 ret = fdt_increase_size(blob, 4096);
1271 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1274 karo_fdt_enable_node(blob, "stk5led", 0);
1276 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1277 fdt_fixup_ethernet(blob);
1279 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1280 ARRAY_SIZE(tx6_touchpanels));
1281 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1282 karo_fdt_fixup_flexcan(blob, stk5_v5);
1284 karo_fdt_update_fb_mode(blob, video_mode);
1286 #endif /* CONFIG_OF_BOARD_SETUP */